Publications

Books

  1. Emerging Nanoelectronics: Life With and After CMOS, Vol. 1,
    Adrian M. Ionescu and Kaustav Banerjee
    Springer (Kluwer), ISBN: 1-4020-7533-2, 622 pp. (2005)
  2. Emerging Nanoelectronics: Life With and After CMOS, Vol. 2
    Adrian M. Ionescu and Kaustav Banerjee
    Springer (Kluwer), ISBN: 1-4020-7915-X, 340 pp. (2005)
  3. Emerging Nanoelectronics: Life With and After CMOS, Vol. 3
    Adrian M. Ionescu and Kaustav Banerjee
    Springer (Kluwer), ISBN: 1-4020-7916-8, 428 pp. (2005)

Book Chapters

  1. Carbon Integrated Electronics
    Hong Li, Yasin Khatami, Deblina Sarkar, Jiahao Kang, Chuan Xu, Wei Liu, and Kaustav Banerjee
    in Intelligent Integrated Systems: Technologies, Devices and Architectures. Ed: S. Deleonibus, WSPC-Pan Stanford (Singapore) Publishers, 2013 (in press).
  2. VLSI Technology and Circuits
    K. Banerjee and S. Ikeda
    in Guide to State-of-the-Art Electron Devices, Ed. J. Burghartz, John Wiley & Sons, Ltd, ISBN: 978-1-1183-4726-3, 2013 (in press).
  3. NEMS based Ultra Energy-Efficient Digital ICs: Materials, Device Architectures, Logic Implementation, and Manufacturability
    H. F. Dadgour and K. Banerjee
    Chapter 10 in Microelectronics to Nanoelectronics: Materials, Devices & Manufacturability. Ed: Anupama B. Kaul, CRC Press, ISBN 9781466509542, July 2012.
  4. Accurate Calculations of the High-frequency Impedance Matrix for VLSI Interconnects and Inductors above a Multi-layer Substrate: A VARPRO success story
    N. Srivastava, R. Suaya, V. Pereyra and K. Banerjee
    in Exponential Data Fitting and its Applications, Editors: V. Pereyra and G. Scherer. Bentham Science Publishers, ISBN: 978-1-60805-048-2, 2010.
  5. Thermal Challenges of 3-D ICs
    Sheng-Chih Lin and Kaustav Banerjee
    in Wafer Level 3-D ICs Process Technology, Editors: Chuan Seng Tan, Ronald J. Gutmann, L. Rafael Reif, Springer,ISBN: 978-0-387-76532-7, 2008
  6. 3D ICs DSM Interconnect Performance Modeling and Analysis
    S. Souri, T-Y. Chiang, P. Kapur, K. Banerjee and K. C. Saraswat
    in Interconnect Technology and Design for Gigascale Integration, Editors: Jeffrey A. Davis and James D. Meindl, Springer, ISBN: 1-4020-7606-1, 2003

Journal Papers

  1. Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability
    Chuan Xu, Seshadri K. Kolluri, Kazuhiko Endo and Kaustav Banerjee
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. xx, pp. xx-yy, 2013 (in press).
  2. Impact-Ionization Field-Effect-Transistor Based Biosensors for Ultra-Sensitive Detection of Biomolecules
    Deblina Sarkar, Harald Gossner, Walter Hansch and Kaustav Banerjee
    Applied Physics Letters, Vol. 102, 2013 (in press)
  3. Role of Metal Contacts in Designing High-Performance Monolayer n-Type WSe2 Field-Effect-Transistors
    Wei Liu, Jiahao Kang, Deblina Sarkar, Yasin Khatami, Debdeep Jena and Kaustav Banerjee
    Nano Letters, Vol. 13, no. 5, pp. 1983-1990, 2013. []
  4. Graphene nanoribbon based negative resistance device for ultra-low voltage digital logic applications
    Yasin Khatami, Jiahao Kang, and Kaustav Banerjee
    Applied Physics Letters, Vol. 102, No.4 , 043114, 2013. []
  5. Tunnel-Field-Effect-Transistor Based Gas-Sensor: Introducing Gas Detection with a Quantum-Mechanical Transducer
    Deblina Sarkar, Harald Gossner, Walter Hansch and Kaustav Banerjee
    Applied Physics Letters, Vol. 102, No. 2, 023110, 2013. []
  6. Physical Modeling of the Capacitance and Capacitive Coupling-Noise of Through-Oxide Vias in FDSOI Based Ultra-High Density 3-D ICs
    Chuan Xu and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 60, No. 1, pp. 123-131, 2013 []
  7. Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs with Multiple Substrates
    Chuan Xu, Navin Srivastava, Roberto Suaya and Kaustav Banerjee
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, No. 11, pp. 1698-1710, 2012. []
  8. Some Clarifications on “Compact Modeling and Analysis of Through-Si-Via Induced Electrical Noise Coupling in Three-Dimensional ICs
    Chuan Xu, Roberto Suaya and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 59, No. 10, pp. 2861-2862, 2012 []
  9. Metal to Multi-Layer Graphene Contact--Part II: Analysis of Contact Resistance
    Yasin Khatami, Hong Li, Chuan Xu, and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 59, No. 9, pp. 2453-2460, 2012. []
  10. Metal to Multi-Layer Graphene Contact--Part I: Contact Resistance Modeling
    Yasin Khatami, Hong Li, Chuan Xu, and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 59, No. 9, pp. 2444-2452, 2012. []
  11. Top Illuminated Inverted Organic UV Photosensors With Single Layer Graphene Electrodes
    Martin Burkhardt, Wei Liu, Christopher G. Shuttle, Kaustav Banerjee, and Michael L. Chabinyc
    Applied Physics Letters, Vol. 101, 033302, 2012. []
  12. Proposal for Tunnel-Field-Effect-Transistor as Ultra-Sensitive and Label-Free Biosensors
    Deblina Sarkar and Kaustav Banerjee
    Applied Physics Letters, 100, No. 14, 143108, 2012 []
  13. Synthesis of High-Quality Monolayer and Bilayer Graphene on Copper using Chemical Vapor Deposition
    Wei Liu, Hong Li, Chuan Xu, Yasin Khatami and Kaustav Banerjee
    CARBON, Vol. 49, No. 13, pp. 4122-4130, Nov. 2011. []
  14. Vertically Stacked and Independently Controlled Twin-Gate MOSFETs on a Single Si-Nanowire
    Xiang Li, Zhixian Chen, Nansheng Shen, Deblina Sarkar, Navab Singh, Kaustav Banerjee, Guo-Qiang Lo and Dim-Lee Kwong
    IEEE Electron Device Letters, Vol. 32, No. 11, pp. 1492-1494, Nov. 2011. []
  15. CMOS Compatible Vertical Silicon Nanowire Gate-All-Around p-type Tunneling FETs with ≤50 mV/decade Subthreshold Swing
    Ramanathan Gandhi, Zhixian Chen, Navab Singh, Kaustav Banerjee and Sungjoo Lee
    IEEE Electron Device Letters, Vol. 32, No. 11, pp. 1504-1506, Nov. 2011. []
  16. Compact Modeling and Analysis of Through-Si-Via Induced Electrical Noise Coupling in 3-D ICs
    Chuan Xu, Roberto Suaya and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 58, No. 11, pp. 4024-4034, Nov. 2011 []
  17. A Physical Model for Work-Function Variation in Ultra-Short Channel Metal-Gate MOSFETs
    Seid Hadi Rasouli, Chuan Xu, Navab Singh and Kaustav Banerjee
    IEEE Electron Device Letters, Vol. 32, No. 11, pp. 1507-1509, Nov. 2011. []
  18. A Fully Analytical Model for the Series Impedance of Through-Silicon Vias with Consideration of Substrate Effects and Coupling with Horizontal Interconnects
    Chuan Xu, Vassilis Kourkoulos, Roberto Suaya and Kaustav Banerjee
    IEEE Transactions on Electron Devices, vol. 58, no. 10, pp. 3529-3540, Oct. 2011. []
  19. Metallic-Nanoparticle Assisted Enhanced Band-to-Band Tunneling Current
    Deblina Sarkar and Kaustav Banerjee
    Applied Physics Letters, Vol. 99, No. 13, p. 133116, Sept 26, 2011. []
  20. Carbon Nanotube Vias: Does Ballistic Electron-Phonon Transport Imply Improved Performance and Reliability?
    Hong Li, Navin Srivastava, Jun-Fa Mao, Wen-Yan Yin and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 58, no. 8, pp. 2689-2701, Aug. 2011. []
  21. Grain-Orientation Induced Quantum Confinement Variation in FinFETs and Multi-Gate Ultra-Thin Body CMOS Devices and Implications for Digital Design
    Seid Hadi Rasouli, Kazuhiko Endo, Jone F. Chen, Navab Singh and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Special Issue on "Characterization of Nano CMOS Variability by Simulation and Measurements," vol. 58, no. 8, pp. 2282-2292, Aug. 2011. []
  22. Vertical Si-Nanowire n-Type Tunneling FETs With Low Subthreshold Swing (≤ 50 mV/decade) at Room Temperature
    Ramanathan Gandhi, Zhixian Chen, Navab Singh, Kaustav Banerjee, and Sungjoo Lee
    IEEE Electron Device Letters, vol. 32, no. 4, pp. 437-439, April 2011 []
  23. High-Frequency Behavior of Graphene-Based Interconnects—Part I: Impedance Modeling
    Deblina Sarkar, Chuan Xu, Hong Li, and Kaustav Banerjee
    IEEE Transactions on. Electron Devices, vol. 58, no. 3, pp. 843-852, March 2011. []
  24. High-Frequency Behavior of Graphene-Based Interconnects—Part II: Impedance Analysis and Implications for Inductor Design
    Deblina Sarkar, Chuan Xu, Hong Li, and Kaustav Banerjee
    IEEE Transactions on Electron Devices, vol. 58, no. 3, pp. 853-859, March 2011. []
  25. Electron-hole Duality During Band-to-Band Tunneling Process in Graphene-Nanoribbon Tunnel-Field-Effect Transistors
    Deblina Sarkar, Michael Krall, and Kaustav Banerjee
    Applied Physics Letters, Vol. 97, No. 26, p. 263109, Dec 27, 2010. []
  26. Compact AC Modeling and Performance Analysis of Through-Silicon Vias (TSVs) in 3-D ICs
    Chuan Xu, Hong Li, Roberto Suaya and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 57, No. 12, pp. 3405-3417, Dec. 2010. []
  27. Design Optimization of FinFET Domino Logic Considering the Width Quantization Property
    Seid Hadi Rasouli, Hamed F. Dadgour, Kazuhiko Endo, Hanpei Koike, and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 57, No. 11, pp. 2934-2943, Nov. 2010. []
  28. A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-in Dynamic Gates
    Hamed Dadgour and Kaustav Banerjee
    IEEE Transactions on VLSI Systems, Vol. 18, No. 11, pp. 1567-1577, Nov. 2010. []
  29. A Novel Enhanced Electric-Field Impact-Ionization MOS Transistor
    Deblina Sarkar, Navab Singh and Kaustav Banerjee
    IEEE Electron Device Letters, vol. 31, no. 11, pp. 1175-1177, Nov. 2010. []
  30. A Thermal Simulation Process Based on Electrical. Modeling for Complex Interconnect, Packaging and 3DI Structures
    Lijun Jiang, Chuan Xu, Barry J. Rubin, Alan J. Weger, Alina Deutsch, Howard Smith, Alain Caron, and Kaustav Banerjee
    IEEE Trans. Advanced Packaging, Vol. 33, No. 4, pp. 777-786, Nov. 2010. []
  31. Grain-Orientation Induced Work-Function Variation in Nanoscale Metal-Gate Transistors––Part I: Modeling, Analysis, and Experimental Validation
    Hamed F. Dadgour, Kazuhiko Endo, Vivek De, and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 57, No. 10, pp. 2504-2514, 2010. []
  32. Grain-Orientation Induced Work-Function Variation in Nanoscale Metal-Gate Transistors––Part II: Implications for Process, Device, and Circuit Design
    Hamed F. Dadgour, Kazuhiko Endo, Vivek De, and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 57, No. 10, pp. 2515-2525, 2010. []
  33. Carbon Nanomaterials: The Ideal Interconnect Technology for Next-Generation ICs
    Hong Li, Chuan Xu, and Kaustav Banerjee
    IEEE Design and Test of Computers, Special Issue on Emerging Interconnect Technologies for Gigascale Integration, pp. 20-31, July/August, 2010. []
    INVITED
  34. Effect of Grain Orientation on NBTI Variation and Recovery in Emerging Metal-Gate Devices
    Seid Hadi Rasouli and Kaustav Banerjee
    IEEE Electron Device Letters, Vol. 31, No. 8, pp. 794-796, Aug 2010. []
  35. Corrections to “Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate”
    Navin Srivastava, Chuan. Xu, Roberto Suaya, and Kaustav Banerjee
    IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 29, No. 5, pp. 849-849, May 2010. []
  36. Steep Subthreshold Slope n- and p-type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits
    Yasin Khatami and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 56, No. 11, pp. 2752-2761, Nov. 2009 []
  37. Hybrid NEMS-CMOS Integrated Circuits: A Novel Strategy for Energy-Efficient Designs
    Hamed Dadgour and Kaustav Banerjee
    IET Transactions on Computers and Digital Techniques—Special Issue on Advances in Nanoelectronics Circuits and Systems, Vol. 3, No. 6, pp. 593-608, Nov. 2009 []
  38. High-Frequency Analysis of Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design
    Hong Li and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 56, No. 10, pp. 2202-2214, Oct 2009 []
  39. Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status and Prospects
    Hong Li, Chuan Xu, Navin Srivastava, and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Special Issue on Compact Interconnect Models for Gigascale Integration, Vol. 56, No. 9, pp. 1799-1821, Sep 2009. []
    INVITED AND HIGHLIGHTED ON THE JOURNAL COVERPAGE
  40. Modeling, Analysis and Design of Graphene Nano-Ribbon Interconnects
    Chuan Xu, Hong Li, and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol.56, No.8, pp. 1567-1578, Aug 2009 []
  41. On the Applicability of Single-Walled Carbon Nanotubes as VLSI Interconnections
    Navin Srivastava, Hong Li, Franz Kreupl, and Kaustav Banerjee
    IEEE Transactions on Nanotechnology, Vol. 8, No. 4, pp. 542-559, July 2009 []
  42. Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multi-layer Conductive Substrate
    Navin Srivastava, Roberto Suaya and Kaustav Banerjee
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, No. 7, pp. 1047-1060, July 2009 []
  43. Accurate Intrinsic Gate Capacitance Model for Carbon Nanotube-Array Based FETs Considering Screening Effect
    Chaitanya Kshirsagar, Hong Li, Tom Kopley, and Kaustav Banerjee
    IEEE Electron Device Letters, Vol. 29, No. 12, pp. 1408-1411, Dec. 2008 []
  44. A Design-Specific and Thermally-Aware Methodology for Trading-off Power and Performance in Leakage-Dominant CMOS Technologies
    Sheng-Chih Lin and Kaustav Banerjee
    IEEE Transactions on Very Large Scale Integration Systems, Vol. 16, No. 11, pp. 1488-1498, Nov. 2008 []
  45. Circuit Modeling and Performance Analysis of Multi-Walled Carbon Nanotube Interconnects
    Hong Li, Wen-Yan Yin, Kaustav Banerjee, and Jun-Fa Mao
    IEEE Transactions on Electron Devices, Vol. 55, No. 6, pp. 1328-1337, 2008 []
  46. Cool Chips: Opportunities and Implications for Power and Thermal Management
    Sheng-Chih Lin and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Special Issue on Device Technologies and Circuit Techniques for Power Management, Vol. 55, No. 1, pp. 245-255, 2008 []
    HIGHLIGHTED ON THE JOURNAL COVER
  47. A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part I: Electrothermal Couplings and Full-Chip Package Thermal Model
    Sheng-Chih Lin, Greg Chrysler, Ravi Mahajan, Vivek De and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 54, No. 12, pp. 3342-3350, 2007 []
  48. A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part II: Implementation and Implications for Power Estimation and Thermal Management
    Sheng-Chih Lin, Greg Chrysler, Ravi Mahajan, Vivek De and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 54, No. 12, pp. 3351-3360, 2007 []
  49. A Statistical Framework for Estimation of Full-Chip Leakage-Power Distribution under Parameter Variations
    Hamed Dadgour, Sheng-Chih Lin and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 54, No. 11, pp. 2930-2945, Nov. 2007 []
  50. 3D-Integration for Introspection
    Shashidhar Mysore, Banit Agrawal, Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee and Timothy Sherwood
    IEEE Micro: Micro's Top Picks from Computer Architecture Conferences (IEEE Micro - top pick), pp. 77-83, January-February 2007 []
  51. Scaling Analysis of Multilevel Interconnect Temperatures in High Performance ICs
    Sungjun Im, Navin Srivastava, Kaustav Banerjee and Kenneth E. Goodson
    IEEE Transactions on Electron Devices, Vol. 52, No. 12, pp. 2710-2719, 2005 []
  52. Supply and Power Optimization in Leakage Dominant Technologies
    Man Lung Mui, Kaustav Banerjee and Amit Mehrotra
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 9, pp. 1362-1371, 2005 []
  53. Modeling and Analysis of Non-Uniform Substrate Temperature Effects on Global ULSI Interconnects
    Amir H. Ajami, Kaustav Banerjee and Massoud Pedram
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 6, pp. 849-861, 2005 []
  54. Mechanisms Leading to Erratic Snapback Behavior in Bipolar Junction Transistors with Base Emitter Shorted
    Amitabh Chatterjee, Ronald D. Schrimpf, Sameer Pendharkar and Kaustav Banerjee
    Journal of Applied Physics, Vol. 97, 084504, April 15, 2005 []
  55. Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI
    Amir H. Ajami, Kaustav Banerjee and Massoud Pedram
    International Journal of Analog Integrated Circuits and Signal Processing, Vol. 42, No. 3, pp. 277-290, Springer, 2005 []
  56. Analytical Modelling of Single Electron Transistor (SET) for Hybrid CMOS-SET Analog IC Design
    Santanu Mahapatra, Vaibhav Vaish, Christoph Wasshuber, Kaustav Banerjee and Adrian Ionescu
    IEEE Transactions on Electron Devices, Vol. 51, No. 11, pp. 1772-1782, Nov. 2004 []
  57. Interconnect Challenges for Nanoscale Electronic Circuits
    Navin Srivastava and Kaustav Banerjee
    TMS Journal of Materials (JOM), Special Issue on Nanoelectronics, Vol. 56, No. 10, pp. 30-31, October 2004 []
    INVITED
  58. Modeling Techniques and Verification Methodologies for Substrate Coupling Effects in Mixed-Signal System-on-Chip Designs
    Adil Koukab, Kaustav Banerjee and Michel Declercq
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 6, pp. 823-836, 2004 []
  59. A Global Interconnect Optimization Scheme for Nanometer Scale VLSI with Implications for Latency, Bandwidth and Power Dissipation
    Man Lung Mui, Kaustav Banerjee and Amit Mehrotra
    IEEE Transactions on Electron Devices, Vol. 51, No. 2, pp. 195-203, February 2004 []
  60. An Interconnect Scaling Scheme with Constant On-Chip Inductive Effects
    Kaustav Banerjee and Amit Mehrotra
    International Journal of Analog Integrated Circuits and Signal Processing, Vol. 35, pp. 97–105, 2003 []
  61. Analysis of Nonuniform ESD Current Distribution in Deep Submicron NMOS Transistors
    Kwang-Hoon Oh, Charvaka Duvvury, Kaustav Banerjee and Robert W. Dutton
    IEEE Transactions on Electron Devices, Vol. 49, No. 12, pp. 2171-2182, December 2002 []
  62. Impact of Gate-to-Contact Spacing on ESD Performance of Salicided Deep Submicron NMOS Transistors
    Kwang-Hoon Oh, Charvaka Duvvury, Kaustav Banerjee and Robert W. Dutton
    IEEE Transactions on Electron Devices, Vol. 49, No. 12, pp. 2183-2192, December 2002 []
  63. A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs
    Kaustav Banerjee and Amit Mehrotra
    IEEE Transactions on Electron Devices, Vol. 49, No. 11, pp. 2001-2007, November 2002 []
  64. Analysis and Design of Distributed ESD Protection Circuits for High-Speed Mixed-Signal and RF ICs
    Choshu Ito, Kaustav Banerjee and Robert W. Dutton
    IEEE Transactions on Electron Devices, Vol. 49, No. 8, pp. 1444-1454, August 2002 []
  65. Analysis of On-Chip Inductance Effects for Distributed RLC Interconnects
    Kaustav Banerjee and Amit Mehrotra
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 8, pp. 904-915, August 2002 []
  66. A Quasi-Analytical SET Model for Few Electron Circuit Simulation
    Santanu Mahapatra, Adrian Mihai Ionescu and Kaustav Banerjee
    IEEE Electron Device Letters, Vol. 23, No. 6, pp. 366-368, June 2002 []
  67. Analysis of Gate-Bias-Induced Heating Effects in Deep-Submicron ESD Protection Designs
    Kwang-Hoon Oh, Charvaka Duvvury, Kaustav Banerjee and Robert W. Dutton
    IEEE Transactions on Devices, Materials and Reliability. Vol. 2, No. 2, pp. 36-42, June 2002 []
  68. SET-based Quantiser Circuit for Digital Communications
    Santanu Mahapatra, Adrian Mihai Ionescu, Kaustav Banerjee and Michel Declercq
    IEE Electronics Letters, Vol. 38, No. 10, pp. 443-445, May 2002 []
  69. Analytical Thermal Model for Multilevel VLSI Interconnects Incorporating Via Effect
    Ting-Yen Chiang, Kaustav Banerjee and Krishna C. Saraswat
    IEEE Electron Device Letters, Vol. 23, No. 1, pp. 31-33, Jan. 2002 []
  70. Global (Interconnect) Warming
    Kuastav Banerjee and Amit Mehrotra
    IEEE Circuits and Devices Magazine, Vol. 17, Issue 5, pp. 16-32, September 2001 []
    INVITED
  71. 3-D ICs: A Novel Chip Design for Improving Deep Submicrometer Interconnect Performance and Systems-on-Chip Integration
    Kaustav Banerjee, Shukri J. Souri, Pawan Kapur, and Krishna C. Saraswat
    Proceedings of the IEEE, Special Issue, Interconnections- Addressing The Next Challenge of IC Technology, Vol. 89, No. 5, pp. 602-633, May 2001 []
    INVITED
  72. Interconnect Limits on Gigascale Integration (GSI) in the 21st Century
    Jeffrey A. Davis, Raguraman Venkatesan, Alain Kaloyeros, Michael Beylansky, Shukri J. Souri, Kaustav Banerjee, Krishna C. Saraswat, Arifur Rahman, Rafael Reif, and James. D. Meindl
    Proceedings of the IEEE, Special Issue on Limits of Semiconductor Technology, Vol. 89, No. 3, pp. 305- 324, March 2001 []
    INVITED
  73. Thermal Characteristics of Sub-Micron Vias Studied by Scanning Joule Expansion Microscopy
    Masanobu Igeta, Kaustav Banerjee, Guanghua Wu, Chenming Hu, and Arun Majumdar
    IEEE Electron Device Letters, Vol. 21, No. 5, pp. 224-226, May 2000 []
  74. Characterization of Self-Heating in Advanced VLSI Interconnect Lines Based on Thermal Finite Element Simulation
    Sven Rzepka, Kaustav Banerjee, Ekkehard Meusel, and Chenming Hu
    IEEE Transactions on Components, Packaging, and Manufacturing Technology-A, Vol. 21, No. 3, pp. 406-411, 1998 []
  75. High-Current Failure Model for VLSI Interconnects Under Short-PuIse Stress Conditions
    Kaustav Banerjee, Ajith Amerasekera, Nathan Cheung, and Chenming Hu
    IEEE Electron Device Letters, Vol. 18, No. 9, pp. 405-407, 1997 []
  76. The Dependence of W-plug Via EM Performance on Via Size
    Huy A. Le, Kaustav Banerjee, and Joe W. McPherson
    Semiconductor Science and Technology, Vol. 11, pp. 858-864, 1996 []

Invited Conference Papers/Talks

  1. Graphene Based Green Electronics
    K. Banerjee
    International Workshop on Physics of Semiconductors (IWPSD), IIT-Kanpur, India, Dec 18-22, 2011.
    INVITED TALK
  2. Future of Carbon Nanomaterials as Next-Generation Interconnects and Passives Devices
    Hong Li, Chuan Xu, Deblina Sarkar, Yasin Khatami, Wei Liu and Kaustav Banerjee
    IEEE Electrical Design of Advanced Packaging & Systems (EDAPS) Symposium, Hangzhou, China, Dec 12-14, 2011
  3. Some Results Pertaining Electromagnetic Characterization and Model Building for Passive Systems Including TSVs, for 3-D IC’s Applications
    R. Suaya , C. Xu , V Kourkoulos , K Banerjee, Z. Mahmood and L. Daniel
    IEEE Electrical Design of Advanced Packaging & Systems (EDAPS) Symposium, Hangzhou, China, Dec 12-14, 2011.
  4. Graphene Based Green Electronics
    K. Banerjee
    IEEE Electrical Design of Advanced Packaging & Systems (EDAPS) Symposium, Hangzhou, China, Dec 12-14, 2011.
    KEYNOTE
  5. Carbon Based Green Electronics
    K. Banerjee
    ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU 2011), Santa Barbara, CA, March 31-April 1, 2011.
    KEYNOTE
  6. Carbon-Based Green Electronics
    Kaustav Banerjee
    Materials Research Society (MRS) Fall Symposium, Boston, MA, Nov. 29-Dec. 3, 2010. (INVITED)
  7. Prospects of Carbon Nanomaterials for Next-Generation Green Electronics
    K. Banerjee, H. Li, C. Xu, Y. Khatami, H.F. Dadgour, D. Sarkar and W. Liu
    IEEE NANO, Kintex, Seoul, August 17-20, pp. 1-6, 2010.
  8. CAD for Nanoelectronics: Earlier the Better
    K. Banerjee
    IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH’08), June 17-18, 2010, Anaheim, CA PANEL: CAD for Nanoelectronic Circuits and Architectures – Are we there yet?
  9. Carbon based Nanomaterials as Interconnects and Passives for Next-Generation VLSI and 3-D ICs
    K. Banerjee
    IEEE WMED, Boise, Idaho, April 16, 2010
    INVITED TUTORIAL
  10. Carbon Based Active and Passive Devices for Next-Generation ICs
    K. Banerjee, W. Liu, H. Li, Y.Khatami, and C. Xu
    Ultimate Limit of Integration in Silicon (ULIS), Glasgow, Scotland, March 17-19, 2010.
    INVITED--PLENARY
  11. Carbon Nanomaterial based Interconnects and Passives for Next-Generation ICs
    K. Banerjee, H. Li and C. Xu
    XVth International Workshop on Physics of Semiconductor Devices (IWPSD), New Delhi India, Dec. 15-19, 2009
  12. Green Electronics using Graphene based Nanomaterials
    K. Banerjee
    Emerging Technologies in Solid State Devices Workshop, Baltimore, MD, December 5 - 6, 2009
  13. Carbon Based Active and Passive Devices for Next-Generation ICs
    K. Banerjee, H. Dadgour, Y. Khatami, H. Li, C. Xu
    Global COE International Symposium on Silicon Nano Devices in 2030: Prospects by World’s Leading Scientists, Oct. 13-14, Tokyo, 2009
  14. Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status and Prospects
    K. Banerjee, H. Li and C. Xu
    International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, Oct. 7-9, 2009
  15. Prospects of Carbon Nanomaterials in VLSI for Interconnections and Energy Storage
    K. Banerjee, H. Li and C. Xu
    31st Annual EOS/ESD Symposium, Anaheim, CA, Aug 30-Sept 4, 2009
  16. Graphene Based Nanomaterials for VLSI Interconnect and Energy-Storage Applications
    K. Banerjee
    ACM/IEEE System Level Interconnect Prediction (SLIP), San Francisco, CA, July 26, 2009
    INVITED PANEL
  17. Carbon Nanomaterials for Next Generation Interconnects and Passives: Physics, Status and Prospects
    K. Banerjee
    International Electrostatic Discharge Workshop (IEW), Lake Tahoe, CA, May 18-21, 2009
    KEYNOTE
  18. Graphene Based Transistors: Physics, Status and Future Perspectives
    K. Banerjee, Y. Khatami, C. Kshirsagar, S. H. Rasouli
    International Symposium on Physical Design (ISPD), San Diego, CA, March 29-April 1
  19. Carbon Nanomaterials for Next Generation Interconnects and Passives: Physics, Status and Prospects
    K. Banerjee
    18th Materials for Advanced Metallization Conference (MAM), Grenoble, France, March 8-11
  20. CMOS vs. Nano: Comrades or Rivals?
    K. Banerjee
    17th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, CA, Feb 22-24 Panel: CMOS vs. Nano: Comrades or Rivals?
    INVITED PANEL
  21. Current Status and Future Perspectives of Carbon Nanotube Interconnects
    K.Banerjee, H. Li and N. Srivastava
    IEEE EMC Symposium, Detroit, MI, August 18-22, 2008. (INVITED)
  22. Current Status and Future Perspectives of Carbon Nanotube Interconnects
    K. Banerjee, H. Li and N. Srivastava
    IEEE NANO: 8th International Conference on Nanotechnology, pp. 432-436, Arlington, TX, August 18-21, 2008 []
  23. Carbon Nanotube Interconnects for Next Generation ICs
    K. Banerjee
    Summer School on Nanoelectronic Circuits and Tools, EPFL, Lausanne, Switzerland, July 14-18, 2008
    INVITED
  24. Hybrid NEMS-CMOS Circuits
    K. Banerjee
    IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH’08), June 12-13, 2008, Anaheim, CA Panel: Non-CMOS NanoElectronics – Will it ever be real?
    INVITED PANEL
  25. High-Frequency Effects in Carbon Nanotube Interconnects
    K. Banerjee
    12th IEEE Workshop on Signal Propagation on Interconnects (SPI), Avignon, Pope's Palace, France, May 12-15, 2008
    KEYNOTE
  26. Power and Thermal Management in the Nanometer Era
    K. Banerjee
    IEEE CPMT EDAPS, Taipei, Taiwan, December 15-17, 2007
  27. Electrothermal Engineering in the Nanometer Era
    K. Banerjee
    17th ACM Great Lakes Symposium on VLSI (GLSVLSI), Stresa-Lago Maggiore, Italy, March 11-13, 2007
    INVITED TUTORIAL
  28. SoC Communication Architectures: Technology, Current Practice, Research and Trends
    K. Banerjee, L. Benini, N. Dutt, K. Lahiri and S. Pasricha
    VLSI Design Conference, Bangalore, India, Jan. 6-10, 2007
    INVITED TUTORIAL
  29. Can Carbon Nanotubes Extend the Lifetime of On-Chip VLSI Interconnections?
    K. Banerjee
    IEEE-CPMT Electrical Design of Advanced Packaging Systems (EDAPS), Shanghai, China, December 17-19, 2006
  30. Power and Thermal Challenges for 65 nm and Below
    K. Banerjee, P. Coteus and V. De
    IEEE International Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 5-9, 2006
    INVITED TUTORIAL
  31. What are Carbon Nanotubes?
    K. Banerjee
    ACM SIGDA Newsletter, Vol. 36, No. 21, Nov. 2006
  32. Carbon Nanotubes: An Emerging Alternative for On-Chip VLSI Interconnects
    K. Banerjee
    Future Directions in IC and Package Design Workshop, (FDIP), Scottsdale, AZ, Oct. 22, 2006
  33. Prospects for Carbon Nanotube Interconnects
    K. Banerjee
    23rd Advanced Metallization Conference (AMC), San Diego, CA, Oct. 16-19, 2006
  34. Modeling and Extraction of Nanometer Scale Interconnects: Challenges and Opportunities
    R. Suaya, R. Escovar, S. Ortiz, K. Banerjee and N. Srivastava
    23rd Advanced Metallization Conference, San Diego, CA, Oct. 16-19, 2006 []
  35. Thermal Dissipation in Multilayer Devices
    R. V. Joshi, K. Banerjee, T. Smy, K. Guarini, C.T. Chuang and N. Zamadmar
    23rd Advanced Metallization Conference, San Diego, CA, Oct. 16-19, 2006
  36. Can Carbon Nanotubes Extend the Lifetime of On-Chip Electrical Interconnections?
    K. Banerjee, S. Im and N. Srivastava
    IEEE Conference on Nano Networks (Nano-Net), Lausanne, Switzerland, Sept. 14-16, 2006
  37. Are Carbon Nanotubes the Future of VLSI Interconnections?
    K. Banerjee and N. Srivastava
    ACM Design Automation Conference (DAC), pp. 809-814, San Francisco, CA, July 24-28, 2006 []
  38. Emerging Interconnect Technologies based on Carbon Nanotubes
    N. Srivastava and K. Banerjee
    IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 27-29, 2006
    INVITED TUTORIAL
  39. Electrothermal Engineering in the Nanometer Era: From Devices and Interconnects to Circuits and Systems
    K. Banerjee, S-C. Lin, and N. Srivastava
    Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 223-230, Yokohama, Japan, Jan. 24-27, 2006 []
  40. Thermal Modeling of Bonded SOI/3D ICs
    R. V. Joshi, K. Banerjee, T. Smy, K. Guarini, C. T. Chuang, A. Devgan and N. Zamadmar
    Advanced Metallization Conference (AMC), pp. 25-31, Colorado Springs, CO. Sept. 26-29, 2005
  41. Interconnect Modeling and Analysis in the Nanometer Era: Cu and Beyond
    K. Banerjee, S. Im and N. Srivastava
    Advanced Metallization Conference (AMC), Colorado Springs, CO. Sept. 26-29, 2005 []
  42. Nanometer Scale Interconnect Challenges
    K. Banerjee
    State-Of-The-Art Seminar, 21st International VLSI Multilevel Interconnection Conference (VMIC), Hawaii, Sept. 29-Oct. 2, 2004
  43. Nano, Quantum, and Molecular Computing: Are we Ready for the Validation and Test Challenges?
    S. K. Shukla, R. Karri, S. C. Goldstein, F. Brewer, K. Banerjee, and S. Basu
    IEEE International High Level Design Validation and Test Workshop, pp. 3-7, November 12-14, San Francisco, CA, 2003 []
    INVITED
  44. Nanometer Scale Issues for On-Chip Interconnections
    K. Banerjee
    IUMRS-ICAM, Symposium B-1, Si-LSI-Related Materials, Processes and Characterization Technology, Yokohama, Japan, October 8-13, 2003
    INVITED
  45. Thermal Issues in Designing Nanometer Scale Interconnects
    K. Banerjee
    20th International VLSI Multilevel Interconnection Conference (VMIC), Marina Del Rey, CA, September 22-25, 2003
    INVITED
  46. Few Electron Devices: Towards Hybrid CMOS-SET Integrated Circuits
    M. Ionescu, M. J. Declercq, S. Mahapatra, K. Banerjee and J. Gautier
    39th ACM Design Automation Conference (DAC), pp. 88-93, New Orleans, LA, June 10-14, 2002 []
    INVITED
  47. Interconnect Reliability under ESD Conditions: Physics, Models and Design Guidelines
    K. Banerjee
    23rd Annual EOS/ESD Symposium, pp. 191, Portland, Oregon, September 9-13, 2001 []
  48. Analysis and Optimization of Thermal Issues in High-Performance VLSI
    K. Banerjee, M. Pedram and A. H. Ajami
    ACM/SIGDA International Symposium on Physical Design (ISPD), pp. 230-237, Sonoma, CA, April 1-4, 2001 []
    INVITED
  49. Trends for ULSI Interconnections and Their Implications for Thermal, Reliability and Performance Issues
    K. Banerjee
    Seventh International Dielectrics and Conductors for ULSI Multilevel Interconnection Conference (DCMIC), pp. 38-50, Santa Clara, CA, March 5-9, 2001 []
    INVITED
  50. Thermal Effects in ULSI Interconnects
    K. Banerjee
    Fabless Semiconductor Association (FSA) Design Modeling Workshop, Santa Clara, CA, Oct. 11-12, 2000
    INVITED TUTORIAL
  51. 3-D ICs: Motivation, Performance Analysis, and Technology
    K. C. Saraswat, K. Banerjee, A. R. Joshi, P. Kalavade, P. Kapur, and S. J. Souri
    Proc. 26th European Solid-State Circuits Conference (ESSCIRC ‘2000), Stockholm, Sweden, Sept. 19 - 21, 2000
    INVITED
  52. 3-D lCs with Multiple Si Layers: Performance Analysis, and Technology
    K. C. Saraswat, K. Banerjee, A. Joshi. P. Kalavade, S. J. Souri, and V. Subramanian
    197th Meeting of The Electrochemical Society, Toronto, May 14-18, 2000
    INVITED
  53. Performance Analysis and Technology of 3-D ICs
    K. C. Saraswat, S. J. Souri, K. Banerjee, P. Kapur
    ACM International Workshop on System Level Interconnect Prediction (SLIP), pp. 85-90, San Diego, CA, April 8-9, 2000
    INVITED
  54. Thermal Effects in Deep Sub-Micron VLSI Interconnects
    Kaustav Banerjee
    IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 20-22, 2000
    INVITED TUTORIAL
  55. Thermal Effects in Interconnects
    W. Hunter, W-Y. Shih and K. Banerjee
    IEEE Annual International Reliability Physics Symposium (IRPS), Reno, NV, March 30 - April 2, 1998
    INVITED TUTORIAL
  56. High Current Effects in Metal Interconnects
    K. Banerjee, A. Amerasekera, G. Dixit, and C. Hu
    Proceedings of the SRC Topical Research Conference on Reliability, Vanderbilt University, Nashville, Oct. 21-22, 1997
    INVITED

Refereed Conference Papers

  1. A Computational Study of Metal-Contacts to Beyond-Graphene 2D Semiconductor Materials
    Jiahao Kang, Deblina Sarkar, Wei Liu, Debdeep Jena and Kaustav Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 407-410, San Francisco, Dec. 10-12, 2012
  2. ESD Characterization of Atomically-Thin Graphene
    H. Li, C. Russ, W. Liu, D. Johnsson, H. Gossner and K. Banerjee
    34th Annual EOS/ESD Symposium, pp. 1-8, Tucson, AZ, September 9-14, 2012.
  3. Fundamental Limitations of Conventional-FET Biosensors: Quantum-Mechanical-Tunneling to the Rescue
    D. Sarkar and K. Banerjee
    Device Research Conference (DRC), pp. 83-84, Penn State University, University Park, PA, June 18-22, 2012.
  4. Fast Extraction of High-Frequency Parallel Admittance of Through-Silicon-Vias and their Capacitive Coupling-Noise to Active Regions
    C. Xu, R. Suaya and K. Banerjee
    IEEE International Microwave Symposium, Montréal, Canada, June 17-22, 2012
  5. Compact Capacitance and Capacitive Coupling-Noise Modeling of Through-Oxide Vias in FDSOI Based Ultra-High Density 3-D ICs
    C. Xu and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 817-820, Washington DC, Dec. 5-7, 2011.
  6. Demonstration of Vertical Silicon Nanowire Tunnel Field Effect Transistor with Low Subthreshold Slope < 50mV/decade
    R. Gandhi, Z. X. Chen, N. Singh, K. Banerjee, and S. J. Lee
    International Conference on Materials for Advanced Technologies (ICMAT), Singapore, June 26-July 1, 2011.
  7. Impact of Scaling on the Performance and Reliability Degradation of Metal-Contacts in NEMS Devices
    H. F. Dadgour, M. M. Hussain, A. Cassell, N. Singh and K. Banerjee
    IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, April 10-14, pp. 280-289, 2011.
  8. Factors Influencing the Synthesis of Monolayer and Bilayer Graphene on Copper using Chemical Vapor Deposition
    Wei Liu, Hong Li, Chuan Xu and Kaustav Banerjee
    38th Conference on the Physics and Chemistry of Surfaces and Interfaces (PCSI-38), San Diego, CA, January 16-20, 2011.
  9. A Quantitative Inquisition into ESD Sensitivity to Strain in Nanoscale CMOS Protection Devices
    D. Sarkar, S. Thijs, D. Linten, C. Russ, H. Gossner and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 6-8, pp. 808-811, 2010.
  10. Compact Modeling and Analysis of Coupling Noise Induced by Through-Si-Vias in 3-D ICs
    C. Xu, R. Suaya and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 6-8, pp. 178-181, 2010.
  11. Work-function variation induced fluctuation in bias-temperature-instability characteristics of emerging metal-gate devices and implications for digital design
    S. H. Rasouli, K. Endo, and K. Banerjee
    ACM/IEEE International Conf. on Computer-Aided Design (ICCAD), pp. 714-720, San Jose, CA, Nov. 5-8, 2010.
  12. A New Paradigm in the Design of Energy-Efficient Digital Circuits Using Laterally-Actuated Double-Gate NEMS
    H.F. Dadgour, M.M. Hussain and K. Banerjee
    IEEE International Symposium on Low Power Electronics and Design (ISLPED), Austin, TX, August 18-20, pp. 7-12, 2010.
  13. Compact AC Modeling and Performance Analysis of Through-Silicon Vias (TSVs) in 3-D ICs
    C. Xu, H. Li, R. Suaya and K. Banerjee
    28th Progress In Electromagnetics Research Symposium (PIERS), Cambridge, MA, pp.1-2, 2010
  14. Graphene Based Heterostructure Tunnel-FETs for Low-Voltage/High-Performance ICs
    Y. Khatami, M. Krall, H. Li., C. Xu., K. Banerjee
    in Proceedings 68th Device Research Conference (DRC), Notre Dame, IN, June 21-23, 2010, pp. 65-66.
  15. Design and Analysis of Compact Ultra Energy-Efficient Logic Gates Using Laterally-Actuated Double-Electrode NEMS
    H. F. Dadgour, M. M. Hussain, C. Smith and K. Banerjee
    Design Automation Conference (DAC), Anaheim, CA, June 13-18, 2010, pp. 893-896.
  16. AC Conductance Modeling and Analysis of Graphene Nanoribbon Interconnects
    D. Sarkar, C. Xu, H. Li, and K. Banerjee
    in Proceedings 13th IEEE International Interconnect Technology Conference (IITC), San Francisco, CA, June 7-9, pp.1-3, 2010.
  17. An Efficient 3D Green’s Function Approach for Fast Impedance Extraction of Interconnects and Spiral Inductors in CMOS RF/Millimeter-wavelength Circuits
    N. Srivastava, R. Suaya and K. Banerjee
    IEEE International Interconnect Technology Conference (IITC), San Francisco, CA, June 7-9, pp. 1-3, 2010.
  18. A Built-in Aging Detection and Compensation Technique for Improving Reliability of Nanoscale CMOS Designs
    H. Dadgour and K. Banerjee
    IEEE International Reliability Physics Symposium (IRPS), May 2-6, Anaheim, CA, pp. 822-825, 2010.
  19. Aging-Resilient Design of Pipelined Architectures using Novel Detection and Correction Circuits
    H. Dadgour and K. Banerjee
    Design and Test in Europe (DATE), Dresden, Germany March 8-12, pp. 244-249, 2010.
  20. Efficient 3D High-frequency Impedance Extraction for General Interconnects and Inductors Above a Layered Substrate
    N. Srivastava, R. Suaya and K. Banerjee
    Design and Test in Europe (DATE), Dresden, Germany March 8-12, pp. 459-464, 2010.
  21. Single wall carbon nanotube-Aptamer Based Biosensors
    S. H. Varghese, Y. Nakajima, Y. Yoshida, T. Maekawa, T. Hanajiri, K. Banerjee, D. S. Kumar
    7 th International Symposium on Bioscience and Nanotechnology, Tokyo, Japan, December 20-21, 2009.
  22. Impact of Strain Engineering and Channel Orientation on the ESD Performance of Nanometer Scale CMOS Devices
    J. Lu, C. Duvvury, H. Gossner and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), Baltimore, Dec. 6-9, 2009
  23. Compact AC Modeling and Analysis of Cu, W, and CNT based Through-Silicon Vias (TSVs) in 3-D ICs
    C. Xu, H. Li, R. Suaya, K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), Baltimore, Dec. 6-9, 2009
  24. Experimental Investigation of ESD Performance for Strained Silicon Nano-Devices
    D. Sarkar, H. Gossner and K. Banerjee
    ESD Forum, Berlin, Dec. 1-2, 2009
  25. Variability Analysis of FinFET-Based Devices and Circuits Considering Electrical Confinement and Width Quantization
    S.H. Rasouli, K. Endo, and K. Banerjee
    International Conf. on Computer-Aided Design (ICCAD), San Jose, Nov. 2-5, pp. 505-512, 2009
  26. Fast 3-D Thermal Analysis of Complex Interconnect Structures Using Electrical Modeling and Simulation Methodologies
    C. Xu, L. Jiang, S. K. Kolluri, B. J. Rubin, A. Deutsch, H. Smith, K. Banerjee
    International Conf. on Computer-Aided Design (ICCAD), San Jose, Nov. 2-5, pp. 658-665, 2009
  27. Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status and Prospects
    K. Banerjee, H. Li, N. Srivastava and C. Xu
    Progress in Electromagnetics Research Symposium (PIERS), Moscow, Russia, August 18-21, 2009
  28. An Analytical Treatment of High-frequency Impedance Extraction for Interconnects and Inductors in the Presence of a Multi-layer Substrate
    R. Suaya, N. Srivastava and K. Banerjee
    Progress in Electromagnetics Research Symposium (PIERS), Moscow, Russia, August 18-21, 2009
  29. Scaling Analysis of Graphene Nanoribbon Tunnel-FETs
    Y. Khatami and K. Banerjee
    Device Research Conference (DRC), pp. 217-218, Penn State University, University Park, PA, June 22-24, pp. 217-218, 2009
  30. High-Speed Low-Power FinFET Based Domino Logic
    S. H. Rasouli, H. Koike and K. Banerjee
    14th Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, Jan. 19-22, 2009
  31. Graphene Nano-Ribbon (GNR) Interconnects: A Genuine Contender or a Delusive Dream?
    C. Xu, H. Li and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 201-204, San Francisco, Dec. 15-17, 2008 []
  32. High-Frequency Effects in Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design
    H. Li and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 525-528, San Francisco, Dec. 15-17, 2008 []
  33. Scaling and Variability Analysis of CNT-Based NEMS Devices and Circuits with Implications for Process Design
    H. Dadgour, A. M. Cassell and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 529-532, San Francisco, Dec. 15-17, 2008
  34. Modeling and Analysis of Grain-Orientation Effects in Emerging Metal-Gate Devices and Implications for SRAM Reliability
    H. Dadgour, K. Endo, V. De and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 705-708, San Francisco, Dec. 15-17, 2008
  35. Statistical Modeling of Metal-Gate Work-Function Variability in Emerging Device Technologies and Implications for Circuit Design
    H. Dadgour, V. De and K. Banerjee
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 270-277, San Jose, Nov. 10-13, 2008
    Nominated for the BEST PAPER AWARD
  36. Analysis and Implications of Parasitic and Screening Effects on the High-Frequency/RF Performance of Tunneling-Carbon Nanotube FETs
    C. Kshirsagar, M. N. El-Zeftawi and K. Banerjee
    IEEE/ACM Design Automation Conference (DAC), Anaheim, CA, June 8-13, pp. 250-255, 2008
  37. 3D Device Modeling of Damage Due to Filamentation Under an ESD Event in Nanometer Scale Drain Extended NMOS (DE-NMOS)
    A. Chatterjee, S. Pendharkar, H. Gossner, C. Duvvury and K. Banerjee
    IEEE International Reliability Physics Symposium (IRPS), pp. 639-640, Phoenix, AZ, April 27-May 1, 2008
  38. High-Frequency Mutual Impedance Extraction of VLSI Interconnects in the Presence of a Multi-layer Conducting Substrate
    N. Srivastava, R. Suaya and K. Banerjee
    IEEE Design and Test in Europe (DATE), pp.42-431, Munich, Germany, March 10-14, 2008
  39. A Fast Semi-numerical Technique for the Solution of the Poisson-Boltzmann Equation in a Cylindrical Nanowire
    A. Ramu, M. P. Anantram and K. Banerjee
    IEEE International Semiconductor Device Research Symposium (ISDRS), pp. 1-2, College Park, MD, December 12-14, 2007
  40. Modeling and Analysis of Intrinsic Gate Capacitance for Carbon Nanotube Array Based Devices Considering Variaion in Screening Effect and Diameter
    C. Kshirsagar and K. Banerjee
    IEEE International Semiconductor Device Research Symposium (ISDRS), pp. 1-2, College Park, MD, December 12-14, 2007
  41. Performance Analysis of Multi-Walled Carbon Nanotube Based Interconnects
    H. Li, W-Y. Yin, J-F. Mao and K. Banerjee
    IEEE International Semiconductor Device Research Symposium (ISDRS), pp. 1-2, College Park, MD, December 12-14, 2007
  42. A Microscopic Understanding of Nanometer Scale DENMOS Failure Mechanism Under ESD Conditions
    A. Chatterjee, S. Pendharkar, Y-Y. Lin, C. Duvvury and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 181-184, Washington DC, Dec. 10-12, 2007
  43. Modeling and Analysis of Self-Heating in FinFET Devices for Improved Circuit and EOS/ESD Performance
    S. Kolluri, K. Endo, E. Suzuki and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 177-180, Washington DC, Dec. 10-12, 2007
  44. Carbon Nanotube Vias: A Reality Check
    H. Li, N. Srivastava, J-F. Mao, W-Y. Yin and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 207-210, Washington DC, Dec. 10-12, 2007 []
  45. Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications
    H. F. Dadgour and K. Banerjee
    IEEE/ACM Design Automation Conference (DAC), pp. 306-311, San Diego, CA, June 4-8, 2007
  46. Nano-enhanced Architectures: Using Carbon Nanotube Interconnects in Cache Design
    B. Agrawal, N. Srivastava, F. T. Chong, K. Banerjee and T. Sherwood
    4th Workshop on Non-Silicon Computing (NSC-4) held in conjunction with the International Symposium on Computer Architecture (ISCA'07 workshop), San Diego, California, June 2007
  47. An Insight into the High Current ESD Behavior of Drain Extended NMOS (DENMOS) Devices in Nanometer Scale CMOS Technologies
    A. Chatterjee, S. Pendharkar, Y-Y. Lin , C. Duvvury and K. Banerjee
    IEEE International Reliability Physics Symposium (IRPS), pp. 608-609, Phoenix, AZ, April 15-19, 2007
  48. An Electrothermally-Aware Full-Chip Substrate Temperature Gradient Evaluation Methodology for Leakage Dominant Technologies with Implications for Power Estimation and Hot-Spot Management
    S-C. Lin and K. Banerjee
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 568-574, San Jose, CA, Nov. 5-9, 2006 []
  49. Introspective 3-D Chips
    S. C. Mysore, B. Agrawal, N. Srivastava, S-C. Lin, K. Banerjee and T. Sherwood
    International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pp. 264-273, San Jose, CA, Oct. 25-25, 2006 []
    IEEE MICRO Top Pick
  50. A Thermally-Aware Performance Analysis of Vertically Integrated (3-D) Processor-Memory Hierarchy
    G. Loi, B. Agarwal, N. Srivastava, S-C. Lin, T. Sherwood and K. Banerjee
    ACM Design Automation Conference (DAC), pp. 991-996, San Francisco, CA, July 24-28, 2006 []
  51. A Novel Variation-Aware Low-Power Keeper Architecture for Wide Fan-in Dynamic Gates
    H. F. Dadgour, R. V. Joshi and K. Banerjee
    ACM Design Automation Conference (DAC), pp. 977-982, San Francisco, CA, July 24-28, 2006 []
  52. New Physical Insight and Modeling of Second Breakdown (It2) Phenomenon in Advanced ESD Protection Devices
    A. Chatterjee, C. Duvvury and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 203-206, Washington DC, Dec. 5-7, 2005 []
  53. Carbon Nanotube Interconnects: Implications for Performance, Power Dissipation and Thermal Management
    N. Srivastava, R. V. Joshi and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 257-260, Washington DC, Dec. 5-7, 2005 []
  54. Analysis and Implications of IC Cooling for Deep Nanometer Scale CMOS Technologies
    S-C. Lin, R. Mahajan, V. De and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 1041-1044, Washington DC, Dec. 5-7, 2005 []
    HIGHLIGHTED PAPER OF IEDM 2005
  55. Performance Analysis of Carbon Nanotube Interconnects for VLSI Applications
    N. Srivastava and K. Banerjee
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 383-390, San Jose, CA, November 6-10, 2005 []
  56. Thermal Scaling Analysis of Multilevel Cu/Low-k Interconnect Structures in Deep Nanometer Scale Technologies
    S. Im, N. Srivastava, K. Banerjee and K. E. Goodson
    Proceedings of the 22nd International VLSI Multilevel Interconnect Conference (VMIC), pp. 525-530, Fremont, CA, October 3-6, 2005 []
    OUTSTANDING STUDENT PAPER AWARD
  57. A Thermally Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs
    S-C. Lin, N. Srivastava and K. Banerjee
    IEEE International Conference on Computer Design (ICCD), pp. 411-416, San Jose, October 2-5, 2005 []
  58. A Probabilistic Framework for Power-Optimal Repeater Insertion for Global Interconnects Under Parameter Variations
    V. Wason and K. Banerjee
    International Symposium on Low Power Electronic Design (ISLPED), pp. 131-136, San Diego, CA, August 8-10, 2005 []
    Nominated for the BEST PAPER AWARD
  59. Impact of On-Chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits
    N. Srivastava, X. Qi and K. Banerjee
    IEEE International Symposium on Quality Electronic Design, pp. 346-351, San Jose, CA, March 21-23, (ISQED), 2005, []
  60. Leakage and Variation Aware Thermal Management of Nanometer Scale ICs
    K. Banerjee, S-C. Lin, and V. Wason
    Proceedings of the IMAPS-Advanced Technology Workshop on Thermal Management, Oct. 25-27, Palo Alto, CA, 2004 []
  61. A Comparative Scaling Analysis of Metallic and Carbon Nanotube Interconnections for Nanometer Scale VLSI Technologies
    N. Srivastava and K. Banerjee
    Proceedings of the 21st International VLSI Multilevel Interconnect Conference (VMIC), pp. 393-398, Hawaii, Sept. 29-Oct. 2, 2004 []
  62. A Probabilistic Framework to Estimate Full-Chip Subthreshold Leakage Power Distribution Considering Within-Die and Die-to-Die P-T-V Variations
    S. Zhang, V. Wason and K. Banerjee
    International Symposium on Low Power Electronic Design (ISLPED), pp. 156-161, Newport Beach, CA, August 9-11, 2004 []
  63. Simultaneous Optimization of Supply and Threshold Voltages for Low-Power and High-Performance Circuits in the Leakage Dominant Era
    A. Basu, S-C. Lin, V. Wason, A. Mehrotra and K. Banerjee
    ACM Design Automation Conference (DAC), pp. 884-887, San Diego, CA, June 7-10, 2004 []
  64. Impact of Off-state Leakage Current on Electromigration Design Rules for Nanometer Scale CMOS Technologies
    S-C. Lin, A. Basu, A. Keshavarzi, V. De and K. Banerjee
    IEEE Annual International Reliability Physics Symposium (IRPS), pp. 74-78, Phoenix, AZ, April 25-29, 2004 []
  65. A Comprehensive Analytical Capacitance Model of a Two Dimensional Nanodot Array
    A. Basu, S-C. Lin, C. Wasshuber, A. Ionescu and K. Banerjee
    IEEE International Symposium on Quality Electronic Design (ISQED), pp. 259-264, San Jose, CA, March 22-24, 2004 []
  66. Power Supply Optimization in Sub-130 nm Leakage Dominant Technologies
    Man L Mui, K. Banerjee and A. Mehrotra
    IEEE International Symposium on Quality Electronic Design (ISQED), pp. 409-414, San Jose, CA, March 22-24, 2004 []
  67. A Self-Consistent Junction Temperature Estimation Methodology for Nanometer Scale ICs with Implications for Performance and Thermal Management
    K. Banerjee, S-C. Lin, A. Keshavarzi, S. Narendra and V. De
    IEEE International Electron Devices Meeting (IEDM), pp. 887-890, Washington DC, December 7-10, 2003 []
  68. SETMOS: A Novel True Hybrid SET-CMOS High Current Coulomb Blockade Oscillation Cell for Future Nano-Scale Analog ICs
    S. Mahapatra, V. Pott, S. Ecoffey, A. Schmid, C. Wasshuber, J. W. Tringe, Y. Leblebici, M. Declercq, K. Banerjee and A. M. Ionescu
    IEEE International Electron Devices Meeting (IEDM), pp. 703-706, Washington DC, December 7-10, 2003 []
  69. A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits
    S. Mahapatra, K. Banerjee, F. Pegeon, and A. M. Ionescu
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 497-502, San Jose, CA, November 9-13, 2003 []
  70. A SET Quantizer Circuit Aiming at Digital Communication System
    S. Mahapatra, A. M. Ionescu, K. Banerjee and M. J. Declercq
    IEEE International Symposium on Circuits and Systems (ISCAS), pp. 860-863, Scottsdale, AZ, May 26-29, 2003 []
  71. Teaching Microelectronics in the Silicon ICs Showstopper Zone: A Course on Ultimate Devices and Circuits: Towards Quantum Electronics
    A. M. Ionescu, M. J. Declercq, K. Banerjee and S. Mahapatra
    4th European Workshop on Microelectronics Education (EWME), Baiona, Mancomunidad de Vigo, Spain, May 23-24, 2003 []
  72. Modeling of Temperature Dependent Contact Resistance for Analysis of ESD Reliability
    K-H. Oh, J-H. Chun, K. Banerjee, C. Duvvury, and R. W. Dutton
    41st IEEE Annual International Reliability Physics Symposium (IRPS), pp. 249-255, Dallas, TX, March 30-April 4, 2003 []
  73. Analysis of IR-Drop Scaling with Implications for Deep Submicron P/G Network Designs
    A. H. Ajami, K. Banerjee, A. Mehrotra and M. Pedram
    IEEE International Symposium on Quality Electronic Design (ISQED), pp. 35-40, San Jose, CA, March 24-26, 2003 []
  74. Non-uniform Conduction Induced Reverse Channel Length Dependence of ESD Reliability for Silicided NMOS Transistors
    K-H. Oh, K. Banerjee, C. Duvvury and R. W. Dutton
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 341-344, San Francisco, December 8-11, 2002 []
  75. Via Design and Scaling Strategy for Nanometer Scale Interconnect Technologies
    S. Im, K. Banerjee and K. E. Goodson
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 587-590, San Francisco, December 8-11, 2002 []
  76. Modeling and Analysis of Power Dissipation in Single Electron Logic
    S. Mahapatra, A. M. Ionescu, K. Banerjee and M. J. Declercq
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 323-326, San Francisco, December 8-11, 2002 []
  77. Analysis and Optimization of Substrate Noise Coupling in Single-Chip RF Transceiver Design
    A. Koukab, K. Banerjee, and M. Declercq
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 309-316, San Jose, CA, November 10-14, 2002 []
  78. Quasi-Analytical Modeling of Drain Current and Conductance of Single Electron Transistors with MIB
    S. Mahapatra, A. M. Ionescu and K. Banerjee
    32nd European Solid-State Device Research Conference (ESSDERC), pp. 391-394, Florence, Italy, September 24-26, 2002 []
  79. Power Dissipation Issues in Interconnect Performance Optimization for Sub-180 nm Designs
    K. Banerjee and A. Mehrotra
    IEEE Symposium on VLSI Circuits, pp. 12-15, Honolulu, HI, June 13-15, 2002 []
  80. Modeling and Analysis of Via Hot Spots and Implications for ULSI Interconnect Reliability
    S. Im, K. Banerjee and K. E. Goodson
    40th IEEE Annual International Reliability Physics Symposium (IRPS), pp. 336-345, Dallas, TX, April 8-11, 2002 []
  81. Investigation of Gate to Contact Spacing Effect on ESD Robustness of Salicided Deep Submicron Single Finger NMOS Transistors
    K-H. Oh, C. Duvvury, K. Banerjee and R. W. Dutton
    40th IEEE Annual International Reliability Physics Symposium (IRPS), pp. 148-155, Dallas, TX, April 8-11, 2002 []
  82. Inductance Aware Interconnect Scaling
    Inductance Aware Interconnect Scaling
    IEEE International Symposium on Quality Electronic Design (ISQED), pp. 43-47, San Jose, CA, March 18-21, 2002 []
  83. Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET (SG-MOSFET) with a Metal Over-Gate-Architecture
    A. M. Ionescu, V. Pott, R. Fritschi, K. Banerjee, M. J. Declercq, Ph. Renaud, C. Hibert, Ph. Fluckiger and G-A. Racine
    IEEE International Symposium on Quality Electronic Design (ISQED), pp. 496-501, San Jose, CA, March 18-21, 2002 []
  84. 3-D Integrable Optoelectronic Devices for Telecommunications ICs
    P. Dainesi, A. M. Ionescu, L. Thevenaz, K. Banerjee, M. J. Declercq, Ph. Robert, Ph. Renaud, Ph. Fluckiger, C. Hibert and G-A. Racine
    IEEE International Solid State Circuits Conference (ISSCC), pp. 360-361, San Francisco, CA, February, 4-6, 2002 []
  85. Localized Heating Effects and Scaling of Sub-0.18 Micron CMOS Devices
    E. Pop, K. Banerjee, P. Sverdrup, R. Dutton and K. Goodson
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 677-680, Washington, DC, December 3-5, 2001 []
  86. Gate Bias Induced Heating Effect and Implications for the Design of Deep Submicron ESD Protection
    K-H. Oh, C. Duvvury, K. Banerjee and R. W. Dutton
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 315-318, Washington, DC, December 3-5, 2001 []
  87. Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects
    T-Y. Chiang, K. Banerjee and K. C. Saraswat
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 165-172, San Jose, CA, November 4-8, 2001 []
  88. Coupled Analysis of Electromigration Reliability and Performance in ULS1 Signal Nets
    K. Banerjee and A. Mehrotra
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 158-164, San Jose, CA, November 4-8, 2001 []
  89. Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion
    A. H. Ajami, K. Banerjee and M. Pedram
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 44-48, San Jose, CA, November 4-8, 2001 []
  90. Analysis and Optimization of Distributed ESD Protection Circuits for High-Speed Mixed Signal and RF Applications
    C. Ito, K. Banerjee and R. W. Dutton
    23rd Annual EOS/ESD Symposium, pp. 355-363, Portland, OR, September 9-13, 2001 []
  91. Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology RT-Distributed RLC Interconnects
    K. Banerjee and A. Mehrotra
    38th ACM Design Automation Conference (DAC), pp. 798-803, Las Vegas, NV, June 18-22, 2001 []
    BEST PAPER AWARD
  92. Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs
    A. H. Ajami, K. Banerjee, M. Pedram, and L.P.P.P. van Ginneken
    38th ACM Design Automation Conference (DAC), pp. 567-572, Las Vegas, NV, June 18-22, 2001 []
  93. Accurate Analysis of On-Chip Inductance Effects and Implications for Optimal Repeater Insertion and Technology Scaling
    K. Banerjee and A. Mehrotra
    IEEE Symposium on VLSI Circuits, pp. 195-198, Kyoto, Japan, June 14-16, 2001 []
  94. Non-Uniform Chip-Temperature Dependent Signal Integrity
    A. H. Ajami, K. Banerjee and M. Pedram
    IEEE Symposium on VLSI Technology, pp. 145-146, Kyoto, Japan, June 12-14, 2001 []
  95. A New Analytical Thermal Model for Multilevel VLSI Interconnects Incorporating Via Effects
    T-Y Chiang, K. Banerjee and K. C. Saraswat
    IEEE International Interconnect Technology Conference (IITC), pp. 92-94, San Francisco, CA, June 4-6, 2001 []
  96. RF LDMOS Characterization and Its Compact Modeling
    J. Jang, O. Tornblad, T. Arnborg, Q. Chen, K. Banerjee, Z. Yu and R. W. Dutton
    IEEE/MTT-S International Microwave Symposium, pp. 967-970, Phoenix, AZ, May 20-25, 2001 []
  97. 3-D Heterogeneous ICs: A Technology for the Next Decade and Beyond
    K. Banerjee, S. J. Souri, P. Kapur and K. C. Saraswat
    5th IEEE Workshop on Signal Propagation on Interconnects, Venice, Italy, May 13-16, 2001 []
  98. A Fast Analytical Technique for Estimating the Bounds of On-Chip Clock Wire Inductance
    Y-C. Lu, K. Banerjee, M. Celik and R. W. Dutton
    IEEE Custom Integrated Circuits Conference (CICC), pp. 241-244, San Diego, CA, May 6-9, 2001 []
  99. Effects of Non-Uniform Substrate Temperature on the Clock Signal Integrity in High Performance Designs
    A. H. Ajami, M. Pedrarn and K. Banerjee
    IEEE Custom Integrated Circuits Conference (CICC), pp. 233-236, San Diego, CA, May 6-9, 2001 []
  100. Non-uniform Bipolar Conduction in Single Finger NMOS Transistors and Implications for Deep Submicron ESD Design
    K-H. Oh, C. Duvvury, C. Salling, K. Banerjee, and R. W. Dutton
    39th IEEE Annual International Reliability Physics Symposium (IRPS), pp. 226-234, Orlando, FL, April 30-May 3, 2001 []
  101. Analysis and Design of ESD Protection Circuits for High-Frequency/RF Applications
    C. Ito, K. Banerjee and R. W. Dutton
    IEEE International Symposium on Quality Electronic Design (ISQED), pp. 117-122, San Jose, CA, March 26-28, 2001 []
  102. Effect of Via Separation and Low-k Dielectric Materials on the Thermal Characteristics of Cu Interconnects
    T-Y. Chiang, K. Banerjee, K. C. Saraswat
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 261-264, San Francisco, CA, Dec. 11-13, 2000 []
  103. Full Chip Thermal Analysis of Planar (2-D) and Vertically Integrated (3-D) High Performance ICs
    S. Im and K. Banerjee
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 727-730, San Francisco, CA, Dec. 11-13, 2000 []
  104. Advanced Electro-Thermal Modeling and Simulation Techniques for Deep Sub-Micron Devices
    P. G. Sverdrup, O. Tornblad, K. Banerjee, D. Yergeau, Z. Yu, R. W. Dutton, and K. E. Goodson
    Proceedings of TECHCON, Phoenix, AZ, Sept. 21-23, 2000
  105. Sub-Continuum Thermal Simulations of Deep Sub-micron Devices under ESD Conditions
    P. G. Sverdrup, K. Banerjee, C. Dai, W. Shih, R. W. Dutton, and K. E. Goodson
    IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 54-57, Sept. 6-8, Seattle, WA, 2000 []
  106. Multiple Si Layer ICs: Motivation, Performance Analysis, and Design Implications
    S. J. Souri, K. Banerjee, A. Mehrotra, and K. C. Saraswat
    37th ACM Design Automation Conference (DAC), pp. 213-220, June 5-9, Los Angeles, CA, 2000 []
  107. Process and Layout Dependent Substrate Resistance Modeling for Deep Sub-Micron ESD Protection Devices
    X. Y. Zhang, K. Banerjee, A. Amerasekera, V. Gupta, Z. Yu, and R. W. Dutton
    38th IEEE Annual International Reliability Physics Symposium Proceedings (IRPS), pp. 295-303, San Jose, CA, April 10- 13, 2000 []
  108. Quantitative Projections of Reliability and Performance for Low-k/Cu Interconnect Systems
    K. Banerjee, A. Mehrotra, W. Hunter, K. C. Saraswat, K. E. Goodson, and S. S. Wong
    38th IEEE Annual International Reliability Physics Symposium Proceedings (IRPS), pp. 354-358, San Jose, CA, April 10- 13, 2000 []
  109. Microanalysis of VLSI Interconnect Failure Modes under Short-pulse Stress Conditions
    K. Banerjee, D. Y. Kim, A. Amerasekera, C. Hu, S. S. Wong, and K. E. Goodson
    38th IEEE Annual International Reliability Physics Symposium Proceedings (IRPS), pp. 283-288, San Jose, CA, April 10-13, 2000 []
  110. On Thermal Effects in Deep Sub-Micron VLSI Interconnects
    K. Banerjee, A. Mehrotra, A. Sangiovanni-Vincentelli, and C. Hu
    36th ACM Design Automation Conference (DAC), pp. 885-891, New Orleans, LA, June 21-25, 1999 []
  111. Investigation of Self-Heating Phenomenon in Small Geometry Vias Using Scanning Joule-Expansion Microscopy
    K. Banerjee, G. Wu, M. Igeta, A. Amerasekera, A. Majumdar, and C. Hu
    37th IEEE Annual International Reliability Physics Symposium Proceedings (IRPS), pp. 297-302, San Diego, CA, March 23-25, 1999 []
  112. Comparison of E and 1/E TDDB Model for Si02 under Long-Term/Low-Field Test Conditions
    J.W. McPherson, V. Reddy, K. Banerjee, and H. Le
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 171-174, San Francisco, CA, Dec. 6-9, 1998 []
  113. A New Quantitative Model for Deep Submicron Contact Resistance
    K. Banerjee, A. Amerasekara, G. Dixit, and C. Hu
    Proceedings of the TECHON, Las Vegas, NV, 1998
  114. High Current Effects in Silicide films for Sub-0.25 micron VLSI Technologies
    K. Banerjee, A. Amerasekera, J. A. Kittl, and C. Hu
    36th Proceedings of the IEEE Annual International Reliability Physics Symposium (IRPS), pp. 284-292, Reno, NV, March 30 – April 2, 1998 []
  115. Temperature and Current Effects on Small-Geometry-Contact Resistance
    K. Banerjee, A. Amerasekera, G. Dixit, and C. Hu
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 115 -118, Washington DC, Dec. 7-10, 1997 []
  116. Characterization of Self-Heating in Advanced VLSI Interconnect Lines Based on Thermal Finite Element Simulation
    S. Rzepka, K. Banerjee, E. Meusel, and C. Hu
    3rd International Workshop on Thermal Investigations of ICs and Microstructures (THERMINIC), pp. 108-113, Cannes / Cote d'Azur, France, Sept. 21-23, 1997
  117. Characterization of Contact and Via Failure under Short Duration High Pulsed Current Stress
    K. Banerjee, A. Amerasekera, G. Dixit, N. Cheung, and C. Hu
    35th Proceedings of the IEEE Annual International Reliability Physics Symposium (IRPS), pp. 216-220, Denver, CO, April 8-10, 1997 []
  118. Failure Mechanisms of Multi Layered Thin Film Metal Interconnects under a High Current Pulse
    K. Banerjee, A. Amerasekera, N. Cheung, and C. Hu
    MRS Spring Symp., San Francisco, CA, March 31-April 4, 1997
  119. The Effect of Interconnect Scaling and Low-k Dielectric on the Thermal Characteristics of the IC Metal
    K. Banerjee, A. Amerasekera, G. Dixit, and C. Hu
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 65-68, San Francisco, CA, Dec. 8-11, 1996 []
  120. Thermal Analysis of the Fusion Limits of Metal Interconnect under Short Duration Current Pulses
    K. Banerjee, S. Rzepka, A. Amerasekera, N. Cheung, and C. Hu
    Final Report, IEEE International Integrated Reliability Workshop (IRW), pp. 98-102, Lake Tahoe, CA, Oct 20-23, 1996 []
  121. Characterization and Simulation of Self Heating in a Multi Level VLSI Interconnect System under DC and Pulsed Current Conditions
    K. Banerjee, S. Rzepka, A. Amerasekera, and C. Hu
    Proceedings of the SRC TECHCON, Phoenix, AZ, Sept. 1996
  122. Impact of High Current Stress Conditions on VLSI Interconnect Electromigration Reliability Evaluation
    K. Banerjee, L. Ting, N. Cheung, and C. Hu
    Proceedings of the Thirteenth International VLSI Multilevel Interconnection Conference (VMIC), pp. 289- 294, Santa Clara, CA, June 18-20, 1996
  123. Characterization of VLSI Circuit Interconnect Heating and Failure under ESD Conditions
    K. Banerjee, A. Amerasekera, and C. Hu
    34th Proceedings of the IEEE Annual International Reliability Physics Symposium (IRPS), pp. 237-245, Dallas, TX, April 30-May 2, 1996 []

Technical Reports

  1. Thermal Effects in Deep Sub-micron VLSI Interconnects and Implications for Reliability and Performance
    Kaustav Banerjee
    Electronics Research Laboratory, Memorandum no. UCB/ERL M99/48, September 22, 1999