Publications: Refereed Conference Papers

  1. Characterization of VLSI Circuit Interconnect Heating and Failure under ESD Conditions
    K. Banerjee, A. Amerasekera, and C. Hu
    34th Proceedings of the IEEE Annual International Reliability Physics Symposium (IRPS), pp. 237-245, Dallas, TX, April 30-May 2, 1996
  2. Impact of High Current Stress Conditions on VLSI Interconnect Electromigration Reliability Evaluation
    K. Banerjee, L. Ting, N. Cheung, and C. Hu
    Proceedings of the Thirteenth International VLSI Multilevel Interconnection Conference (VMIC), pp. 289- 294, Santa Clara, CA, June 18-20, 1996
  3. Characterization and Simulation of Self Heating in a Multi Level VLSI Interconnect System under DC and Pulsed Current Conditions
    K. Banerjee, S. Rzepka, A. Amerasekera, and C. Hu
    Proceedings of the SRC TECHCON, Phoenix, AZ, Sept. 1996
  4. Thermal Analysis of the Fusion Limits of Metal Interconnect under Short Duration Current Pulses
    K. Banerjee, S. Rzepka, A. Amerasekera, N. Cheung, and C. Hu
    Final Report, IEEE International Integrated Reliability Workshop (IRW), pp. 98-102, Lake Tahoe, CA, Oct 20-23, 1996
  5. The Effect of Interconnect Scaling and Low-k Dielectric on the Thermal Characteristics of the IC Metal
    K. Banerjee, A. Amerasekera, G. Dixit, and C. Hu
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 65-68, San Francisco, CA, Dec. 8-11, 1996
  6. Failure Mechanisms of Multi Layered Thin Film Metal Interconnects under a High Current Pulse
    K. Banerjee, A. Amerasekera, N. Cheung, and C. Hu
    MRS Spring Symp., San Francisco, CA, March 31-April 4, 1997
  7. Characterization of Contact and Via Failure under Short Duration High Pulsed Current Stress
    K. Banerjee, A. Amerasekera, G. Dixit, N. Cheung, and C. Hu
    35th Proceedings of the IEEE Annual International Reliability Physics Symposium (IRPS), pp. 216-220, Denver, CO, April 8-10, 1997
  8. Characterization of Self-Heating in Advanced VLSI Interconnect Lines Based on Thermal Finite Element Simulation
    S. Rzepka, K. Banerjee, E. Meusel, and C. Hu
    3rd International Workshop on Thermal Investigations of ICs and Microstructures (THERMINIC), pp. 108-113, Cannes / Cote d'Azur, France, Sept. 21-23, 1997
  9. Temperature and Current Effects on Small-Geometry-Contact Resistance
    K. Banerjee, A. Amerasekera, G. Dixit, and C. Hu
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 115 -118, Washington DC, Dec. 7-10, 1997
  10. High Current Effects in Silicide films for Sub-0.25 micron VLSI Technologies
    K. Banerjee, A. Amerasekera, J. A. Kittl, and C. Hu
    36th Proceedings of the IEEE Annual International Reliability Physics Symposium (IRPS), pp. 284-292, Reno, NV, March 30 – April 2, 1998
  11. A New Quantitative Model for Deep Submicron Contact Resistance
    K. Banerjee, A. Amerasekara, G. Dixit, and C. Hu
    Proceedings of the TECHON, Las Vegas, NV, 1998
  12. Comparison of E and 1/E TDDB Model for Si02 under Long-Term/Low-Field Test Conditions
    J.W. McPherson, V. Reddy, K. Banerjee, and H. Le
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 171-174, San Francisco, CA, Dec. 6-9, 1998
  13. Investigation of Self-Heating Phenomenon in Small Geometry Vias Using Scanning Joule-Expansion Microscopy
    K. Banerjee, G. Wu, M. Igeta, A. Amerasekera, A. Majumdar, and C. Hu
    37th IEEE Annual International Reliability Physics Symposium Proceedings (IRPS), pp. 297-302, San Diego, CA, March 23-25, 1999
  14. On Thermal Effects in Deep Sub-Micron VLSI Interconnects
    K. Banerjee, A. Mehrotra, A. Sangiovanni-Vincentelli, and C. Hu
    36th ACM Design Automation Conference (DAC), pp. 885-891, New Orleans, LA, June 21-25, 1999
  15. Process and Layout Dependent Substrate Resistance Modeling for Deep Sub-Micron ESD Protection Devices
    X. Y. Zhang, K. Banerjee, A. Amerasekera, V. Gupta, Z. Yu, and R. W. Dutton
    38th IEEE Annual International Reliability Physics Symposium Proceedings (IRPS), pp. 295-303, San Jose, CA, April 10- 13, 2000
  16. Quantitative Projections of Reliability and Performance for Low-k/Cu Interconnect Systems
    K. Banerjee, A. Mehrotra, W. Hunter, K. C. Saraswat, K. E. Goodson, and S. S. Wong
    38th IEEE Annual International Reliability Physics Symposium Proceedings (IRPS), pp. 354-358, San Jose, CA, April 10- 13, 2000
  17. Microanalysis of VLSI Interconnect Failure Modes under Short-pulse Stress Conditions
    K. Banerjee, D. Y. Kim, A. Amerasekera, C. Hu, S. S. Wong, and K. E. Goodson
    38th IEEE Annual International Reliability Physics Symposium Proceedings (IRPS), pp. 283-288, San Jose, CA, April 10-13, 2000
  18. Multiple Si Layer ICs: Motivation, Performance Analysis, and Design Implications
    S. J. Souri, K. Banerjee, A. Mehrotra, and K. C. Saraswat
    37th ACM Design Automation Conference (DAC), pp. 213-220, June 5-9, Los Angeles, CA, 2000
  19. Sub-Continuum Thermal Simulations of Deep Sub-micron Devices under ESD Conditions
    P. G. Sverdrup, K. Banerjee, C. Dai, W. Shih, R. W. Dutton, and K. E. Goodson
    IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 54-57, Sept. 6-8, Seattle, WA, 2000
  20. Advanced Electro-Thermal Modeling and Simulation Techniques for Deep Sub-Micron Devices
    P. G. Sverdrup, O. Tornblad, K. Banerjee, D. Yergeau, Z. Yu, R. W. Dutton, and K. E. Goodson
    Proceedings of TECHCON, Phoenix, AZ, Sept. 21-23, 2000
  21. Effect of Via Separation and Low-k Dielectric Materials on the Thermal Characteristics of Cu Interconnects
    T-Y. Chiang, K. Banerjee, K. C. Saraswat
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 261-264, San Francisco, CA, Dec. 11-13, 2000
  22. Full Chip Thermal Analysis of Planar (2-D) and Vertically Integrated (3-D) High Performance ICs
    S. Im and K. Banerjee
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 727-730, San Francisco, CA, Dec. 11-13, 2000
  23. Analysis and Design of ESD Protection Circuits for High-Frequency/RF Applications
    C. Ito, K. Banerjee and R. W. Dutton
    IEEE International Symposium on Quality Electronic Design (ISQED), pp. 117-122, San Jose, CA, March 26-28, 2001
  24. Non-uniform Bipolar Conduction in Single Finger NMOS Transistors and Implications for Deep Submicron ESD Design
    K-H. Oh, C. Duvvury, C. Salling, K. Banerjee, and R. W. Dutton
    39th IEEE Annual International Reliability Physics Symposium (IRPS), pp. 226-234, Orlando, FL, April 30-May 3, 2001
  25. Effects of Non-Uniform Substrate Temperature on the Clock Signal Integrity in High Performance Designs
    A. H. Ajami, M. Pedrarn and K. Banerjee
    IEEE Custom Integrated Circuits Conference (CICC), pp. 233-236, San Diego, CA, May 6-9, 2001
  26. A Fast Analytical Technique for Estimating the Bounds of On-Chip Clock Wire Inductance
    Y-C. Lu, K. Banerjee, M. Celik and R. W. Dutton
    IEEE Custom Integrated Circuits Conference (CICC), pp. 241-244, San Diego, CA, May 6-9, 2001
  27. 3-D Heterogeneous ICs: A Technology for the Next Decade and Beyond
    K. Banerjee, S. J. Souri, P. Kapur and K. C. Saraswat
    5th IEEE Workshop on Signal Propagation on Interconnects, Venice, Italy, May 13-16, 2001 []
  28. RF LDMOS Characterization and Its Compact Modeling
    J. Jang, O. Tornblad, T. Arnborg, Q. Chen, K. Banerjee, Z. Yu and R. W. Dutton
    IEEE/MTT-S International Microwave Symposium, pp. 967-970, Phoenix, AZ, May 20-25, 2001
  29. A New Analytical Thermal Model for Multilevel VLSI Interconnects Incorporating Via Effects
    T-Y Chiang, K. Banerjee and K. C. Saraswat
    IEEE International Interconnect Technology Conference (IITC), pp. 92-94, San Francisco, CA, June 4-6, 2001
  30. Non-Uniform Chip-Temperature Dependent Signal Integrity
    A. H. Ajami, K. Banerjee and M. Pedram
    IEEE Symposium on VLSI Technology, pp. 145-146, Kyoto, Japan, June 12-14, 2001
  31. Accurate Analysis of On-Chip Inductance Effects and Implications for Optimal Repeater Insertion and Technology Scaling
    K. Banerjee and A. Mehrotra
    IEEE Symposium on VLSI Circuits, pp. 195-198, Kyoto, Japan, June 14-16, 2001
  32. Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology RT-Distributed RLC Interconnects
    K. Banerjee and A. Mehrotra
    38th ACM Design Automation Conference (DAC), pp. 798-803, Las Vegas, NV, June 18-22, 2001
    BEST PAPER AWARD
  33. Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs
    A. H. Ajami, K. Banerjee, M. Pedram, and L.P.P.P. van Ginneken
    38th ACM Design Automation Conference (DAC), pp. 567-572, Las Vegas, NV, June 18-22, 2001
  34. Analysis and Optimization of Distributed ESD Protection Circuits for High-Speed Mixed Signal and RF Applications
    C. Ito, K. Banerjee and R. W. Dutton
    23rd Annual EOS/ESD Symposium, pp. 355-363, Portland, OR, September 9-13, 2001
  35. Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects
    T-Y. Chiang, K. Banerjee and K. C. Saraswat
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 165-172, San Jose, CA, November 4-8, 2001
  36. Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets
    K. Banerjee and A. Mehrotra
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 158-164, San Jose, CA, November 4-8, 2001
  37. Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion
    A. H. Ajami, K. Banerjee and M. Pedram
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 44-48, San Jose, CA, November 4-8, 2001
  38. Localized Heating Effects and Scaling of Sub-0.18 Micron CMOS Devices
    E. Pop, K. Banerjee, P. Sverdrup, R. Dutton and K. Goodson
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 677-680, Washington, DC, December 3-5, 2001
  39. Gate Bias Induced Heating Effect and Implications for the Design of Deep Submicron ESD Protection
    K-H. Oh, C. Duvvury, K. Banerjee and R. W. Dutton
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 315-318, Washington, DC, December 3-5, 2001
  40. 3-D Integrable Optoelectronic Devices for Telecommunications ICs
    P. Dainesi, A. M. Ionescu, L. Thevenaz, K. Banerjee, M. J. Declercq, Ph. Robert, Ph. Renaud, Ph. Fluckiger, C. Hibert and G-A. Racine
    IEEE International Solid State Circuits Conference (ISSCC), pp. 360-361, San Francisco, CA, February, 4-6, 2002
  41. Inductance Aware Interconnect Scaling
    Inductance Aware Interconnect Scaling
    IEEE International Symposium on Quality Electronic Design (ISQED), pp. 43-47, San Jose, CA, March 18-21, 2002
  42. Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET (SG-MOSFET) with a Metal Over-Gate-Architecture
    A. M. Ionescu, V. Pott, R. Fritschi, K. Banerjee, M. J. Declercq, Ph. Renaud, C. Hibert, Ph. Fluckiger and G-A. Racine
    IEEE International Symposium on Quality Electronic Design (ISQED), pp. 496-501, San Jose, CA, March 18-21, 2002
  43. Modeling and Analysis of Via Hot Spots and Implications for ULSI Interconnect Reliability
    S. Im, K. Banerjee and K. E. Goodson
    40th IEEE Annual International Reliability Physics Symposium (IRPS), pp. 336-345, Dallas, TX, April 8-11, 2002
  44. Investigation of Gate to Contact Spacing Effect on ESD Robustness of Salicided Deep Submicron Single Finger NMOS Transistors
    K-H. Oh, C. Duvvury, K. Banerjee and R. W. Dutton
    40th IEEE Annual International Reliability Physics Symposium (IRPS), pp. 148-155, Dallas, TX, April 8-11, 2002
  45. Power Dissipation Issues in Interconnect Performance Optimization for Sub-180 nm Designs
    K. Banerjee and A. Mehrotra
    IEEE Symposium on VLSI Circuits, pp. 12-15, Honolulu, HI, June 13-15, 2002
  46. Quasi-Analytical Modeling of Drain Current and Conductance of Single Electron Transistors with MIB
    S. Mahapatra, A. M. Ionescu and K. Banerjee
    32nd European Solid-State Device Research Conference (ESSDERC), pp. 391-394, Florence, Italy, September 24-26, 2002
  47. Analysis and Optimization of Substrate Noise Coupling in Single-Chip RF Transceiver Design
    A. Koukab, K. Banerjee, and M. Declercq
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 309-316, San Jose, CA, November 10-14, 2002
  48. Modeling and Analysis of Power Dissipation in Single Electron Logic
    S. Mahapatra, A. M. Ionescu, K. Banerjee and M. J. Declercq
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 323-326, San Francisco, December 8-11, 2002
  49. Non-uniform Conduction Induced Reverse Channel Length Dependence of ESD Reliability for Silicided NMOS Transistors
    K-H. Oh, K. Banerjee, C. Duvvury and R. W. Dutton
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 341-344, San Francisco, December 8-11, 2002
  50. Via Design and Scaling Strategy for Nanometer Scale Interconnect Technologies
    S. Im, K. Banerjee and K. E. Goodson
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 587-590, San Francisco, December 8-11, 2002
  51. Analysis of IR-Drop Scaling with Implications for Deep Submicron P/G Network Designs
    A. H. Ajami, K. Banerjee, A. Mehrotra and M. Pedram
    IEEE International Symposium on Quality Electronic Design (ISQED), pp. 35-40, San Jose, CA, March 24-26, 2003
  52. Modeling of Temperature Dependent Contact Resistance for Analysis of ESD Reliability
    K-H. Oh, J-H. Chun, K. Banerjee, C. Duvvury, and R. W. Dutton
    41st IEEE Annual International Reliability Physics Symposium (IRPS), pp. 249-255, Dallas, TX, March 30-April 4, 2003
  53. Teaching Microelectronics in the Silicon ICs Showstopper Zone: A Course on Ultimate Devices and Circuits: Towards Quantum Electronics
    A. M. Ionescu, M. J. Declercq, K. Banerjee and S. Mahapatra
    4th European Workshop on Microelectronics Education (EWME), Baiona, Mancomunidad de Vigo, Spain, May 23-24, 2003 []
  54. A SET Quantizer Circuit Aiming at Digital Communication System
    S. Mahapatra, A. M. Ionescu, K. Banerjee and M. J. Declercq
    IEEE International Symposium on Circuits and Systems (ISCAS), pp. 860-863, Scottsdale, AZ, May 26-29, 2003
  55. A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits
    S. Mahapatra, K. Banerjee, F. Pegeon, and A. M. Ionescu
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 497-502, San Jose, CA, November 9-13, 2003
  56. SETMOS: A Novel True Hybrid SET-CMOS High Current Coulomb Blockade Oscillation Cell for Future Nano-Scale Analog ICs
    S. Mahapatra, V. Pott, S. Ecoffey, A. Schmid, C. Wasshuber, J. W. Tringe, Y. Leblebici, M. Declercq, K. Banerjee and A. M. Ionescu
    IEEE International Electron Devices Meeting (IEDM), pp. 703-706, Washington DC, December 7-10, 2003
  57. A Self-Consistent Junction Temperature Estimation Methodology for Nanometer Scale ICs with Implications for Performance and Thermal Management
    K. Banerjee, S-C. Lin, A. Keshavarzi, S. Narendra and V. De
    IEEE International Electron Devices Meeting (IEDM), pp. 887-890, Washington DC, December 7-10, 2003
  58. A Comprehensive Analytical Capacitance Model of a Two Dimensional Nanodot Array
    A. Basu, S-C. Lin, C. Wasshuber, A. Ionescu and K. Banerjee
    IEEE International Symposium on Quality Electronic Design (ISQED), pp. 259-264, San Jose, CA, March 22-24, 2004
  59. Power Supply Optimization in Sub-130 nm Leakage Dominant Technologies
    Man L Mui, K. Banerjee and A. Mehrotra
    IEEE International Symposium on Quality Electronic Design (ISQED), pp. 409-414, San Jose, CA, March 22-24, 2004
  60. Impact of Off-state Leakage Current on Electromigration Design Rules for Nanometer Scale CMOS Technologies
    S-C. Lin, A. Basu, A. Keshavarzi, V. De and K. Banerjee
    IEEE Annual International Reliability Physics Symposium (IRPS), pp. 74-78, Phoenix, AZ, April 25-29, 2004
  61. Simultaneous Optimization of Supply and Threshold Voltages for Low-Power and High-Performance Circuits in the Leakage Dominant Era
    A. Basu, S-C. Lin, V. Wason, A. Mehrotra and K. Banerjee
    ACM Design Automation Conference (DAC), pp. 884-887, San Diego, CA, June 7-10, 2004
  62. A Probabilistic Framework to Estimate Full-Chip Subthreshold Leakage Power Distribution Considering Within-Die and Die-to-Die P-T-V Variations
    S. Zhang, V. Wason and K. Banerjee
    International Symposium on Low Power Electronic Design (ISLPED), pp. 156-161, Newport Beach, CA, August 9-11, 2004
  63. A Comparative Scaling Analysis of Metallic and Carbon Nanotube Interconnections for Nanometer Scale VLSI Technologies
    N. Srivastava and K. Banerjee
    Proceedings of the 21st International VLSI Multilevel Interconnect Conference (VMIC), pp. 393-398, Hawaii, Sept. 29-Oct. 2, 2004 []
  64. Leakage and Variation Aware Thermal Management of Nanometer Scale ICs
    K. Banerjee, S-C. Lin, and V. Wason
    Proceedings of the IMAPS-Advanced Technology Workshop on Thermal Management, Oct. 25-27, Palo Alto, CA, 2004 []
  65. Impact of On-Chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits
    N. Srivastava, X. Qi and K. Banerjee
    IEEE International Symposium on Quality Electronic Design, pp. 346-351, San Jose, CA, March 21-23, (ISQED), 2005,
  66. A Probabilistic Framework for Power-Optimal Repeater Insertion for Global Interconnects Under Parameter Variations
    V. Wason and K. Banerjee
    International Symposium on Low Power Electronic Design (ISLPED), pp. 131-136, San Diego, CA, August 8-10, 2005
    Nominated for the BEST PAPER AWARD
  67. A Thermally Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs
    S-C. Lin, N. Srivastava and K. Banerjee
    IEEE International Conference on Computer Design (ICCD), pp. 411-416, San Jose, October 2-5, 2005
  68. Thermal Scaling Analysis of Multilevel Cu/Low-k Interconnect Structures in Deep Nanometer Scale Technologies
    S. Im, N. Srivastava, K. Banerjee and K. E. Goodson
    Proceedings of the 22nd International VLSI Multilevel Interconnect Conference (VMIC), pp. 525-530, Fremont, CA, October 3-6, 2005
    OUTSTANDING STUDENT PAPER AWARD
  69. Performance Analysis of Carbon Nanotube Interconnects for VLSI Applications
    N. Srivastava and K. Banerjee
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 383-390, San Jose, CA, November 6-10, 2005
  70. New Physical Insight and Modeling of Second Breakdown (It2) Phenomenon in Advanced ESD Protection Devices
    A. Chatterjee, C. Duvvury and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 203-206, Washington DC, Dec. 5-7, 2005
  71. Carbon Nanotube Interconnects: Implications for Performance, Power Dissipation and Thermal Management
    N. Srivastava, R. V. Joshi and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 257-260, Washington DC, Dec. 5-7, 2005
  72. Analysis and Implications of IC Cooling for Deep Nanometer Scale CMOS Technologies
    S-C. Lin, R. Mahajan, V. De and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 1041-1044, Washington DC, Dec. 5-7, 2005
    HIGHLIGHTED PAPER OF IEDM 2005
  73. A Thermally-Aware Performance Analysis of Vertically Integrated (3-D) Processor-Memory Hierarchy
    G. Loi, B. Agarwal, N. Srivastava, S-C. Lin, T. Sherwood and K. Banerjee
    ACM Design Automation Conference (DAC), pp. 991-996, San Francisco, CA, July 24-28, 2006
  74. A Novel Variation-Aware Low-Power Keeper Architecture for Wide Fan-in Dynamic Gates
    H. F. Dadgour, R. V. Joshi and K. Banerjee
    ACM Design Automation Conference (DAC), pp. 977-982, San Francisco, CA, July 24-28, 2006
  75. Introspective 3-D Chips
    S. C. Mysore, B. Agrawal, N. Srivastava, S-C. Lin, K. Banerjee and T. Sherwood
    International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pp. 264-273, San Jose, CA, Oct. 25-25, 2006
    IEEE MICRO Top Pick
  76. An Electrothermally-Aware Full-Chip Substrate Temperature Gradient Evaluation Methodology for Leakage Dominant Technologies with Implications for Power Estimation and Hot-Spot Management
    S-C. Lin and K. Banerjee
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 568-574, San Jose, CA, Nov. 5-9, 2006
  77. An Insight into the High Current ESD Behavior of Drain Extended NMOS (DENMOS) Devices in Nanometer Scale CMOS Technologies
    A. Chatterjee, S. Pendharkar, Y-Y. Lin , C. Duvvury and K. Banerjee
    IEEE International Reliability Physics Symposium (IRPS), pp. 608-609, Phoenix, AZ, April 15-19, 2007
  78. Nano-enhanced Architectures: Using Carbon Nanotube Interconnects in Cache Design
    B. Agrawal, N. Srivastava, F. T. Chong, K. Banerjee and T. Sherwood
    4th Workshop on Non-Silicon Computing (NSC-4) held in conjunction with the International Symposium on Computer Architecture (ISCA'07 workshop), San Diego, California, June 2007
  79. Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications
    H. F. Dadgour and K. Banerjee
    IEEE/ACM Design Automation Conference (DAC), pp. 306-311, San Diego, CA, June 4-8, 2007
  80. A Microscopic Understanding of Nanometer Scale DENMOS Failure Mechanism Under ESD Conditions
    A. Chatterjee, S. Pendharkar, Y-Y. Lin, C. Duvvury and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 181-184, Washington DC, Dec. 10-12, 2007
  81. Modeling and Analysis of Self-Heating in FinFET Devices for Improved Circuit and EOS/ESD Performance
    S. Kolluri, K. Endo, E. Suzuki and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 177-180, Washington DC, Dec. 10-12, 2007
  82. Carbon Nanotube Vias: A Reality Check
    H. Li, N. Srivastava, J-F. Mao, W-Y. Yin and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 207-210, Washington DC, Dec. 10-12, 2007
  83. A Fast Semi-numerical Technique for the Solution of the Poisson-Boltzmann Equation in a Cylindrical Nanowire
    A. Ramu, M. P. Anantram and K. Banerjee
    IEEE International Semiconductor Device Research Symposium (ISDRS), pp. 1-2, College Park, MD, December 12-14, 2007
  84. Modeling and Analysis of Intrinsic Gate Capacitance for Carbon Nanotube Array Based Devices Considering Variaion in Screening Effect and Diameter
    C. Kshirsagar and K. Banerjee
    IEEE International Semiconductor Device Research Symposium (ISDRS), pp. 1-2, College Park, MD, December 12-14, 2007
  85. Performance Analysis of Multi-Walled Carbon Nanotube Based Interconnects
    H. Li, W-Y. Yin, J-F. Mao and K. Banerjee
    IEEE International Semiconductor Device Research Symposium (ISDRS), pp. 1-2, College Park, MD, December 12-14, 2007
  86. High-Frequency Mutual Impedance Extraction of VLSI Interconnects in the Presence of a Multi-layer Conducting Substrate
    N. Srivastava, R. Suaya and K. Banerjee
    IEEE Design and Test in Europe (DATE), pp.42-431, Munich, Germany, March 10-14, 2008
  87. 3D Device Modeling of Damage Due to Filamentation Under an ESD Event in Nanometer Scale Drain Extended NMOS (DE-NMOS)
    A. Chatterjee, S. Pendharkar, H. Gossner, C. Duvvury and K. Banerjee
    IEEE International Reliability Physics Symposium (IRPS), pp. 639-640, Phoenix, AZ, April 27-May 1, 2008
  88. Analysis and Implications of Parasitic and Screening Effects on the High-Frequency/RF Performance of Tunneling-Carbon Nanotube FETs
    C. Kshirsagar, M. N. El-Zeftawi and K. Banerjee
    IEEE/ACM Design Automation Conference (DAC), Anaheim, CA, June 8-13, pp. 250-255, 2008
  89. Statistical Modeling of Metal-Gate Work-Function Variability in Emerging Device Technologies and Implications for Circuit Design
    H. Dadgour, V. De and K. Banerjee
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 270-277, San Jose, Nov. 10-13, 2008
    Nominated for the BEST PAPER AWARD
  90. Graphene Nano-Ribbon (GNR) Interconnects: A Genuine Contender or a Delusive Dream?
    C. Xu, H. Li and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 201-204, San Francisco, Dec. 15-17, 2008
  91. High-Frequency Effects in Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design
    H. Li and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 525-528, San Francisco, Dec. 15-17, 2008
  92. Scaling and Variability Analysis of CNT-Based NEMS Devices and Circuits with Implications for Process Design
    H. Dadgour, A. M. Cassell and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 529-532, San Francisco, Dec. 15-17, 2008
  93. Modeling and Analysis of Grain-Orientation Effects in Emerging Metal-Gate Devices and Implications for SRAM Reliability
    H. Dadgour, K. Endo, V. De and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 705-708, San Francisco, Dec. 15-17, 2008
  94. High-Speed Low-Power FinFET Based Domino Logic
    S. H. Rasouli, H. Koike and K. Banerjee
    14th Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, Jan. 19-22, 2009
  95. Scaling Analysis of Graphene Nanoribbon Tunnel-FETs
    Y. Khatami and K. Banerjee
    Device Research Conference (DRC), pp. 217-218, Penn State University, University Park, PA, June 22-24, pp. 217-218, 2009
  96. Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status and Prospects
    K. Banerjee, H. Li, N. Srivastava and C. Xu
    Progress in Electromagnetics Research Symposium (PIERS), Moscow, Russia, August 18-21, 2009
  97. An Analytical Treatment of High-frequency Impedance Extraction for Interconnects and Inductors in the Presence of a Multi-layer Substrate
    R. Suaya, N. Srivastava and K. Banerjee
    Progress in Electromagnetics Research Symposium (PIERS), Moscow, Russia, August 18-21, 2009
  98. Variability Analysis of FinFET-Based Devices and Circuits Considering Electrical Confinement and Width Quantization
    S.H. Rasouli, K. Endo, and K. Banerjee
    International Conf. on Computer-Aided Design (ICCAD), San Jose, Nov. 2-5, pp. 505-512, 2009
  99. Fast 3-D Thermal Analysis of Complex Interconnect Structures Using Electrical Modeling and Simulation Methodologies
    C. Xu, L. Jiang, S. K. Kolluri, B. J. Rubin, A. Deutsch, H. Smith, K. Banerjee
    International Conf. on Computer-Aided Design (ICCAD), San Jose, Nov. 2-5, pp. 658-665, 2009
  100. Experimental Investigation of ESD Performance for Strained Silicon Nano-Devices
    D. Sarkar, H. Gossner and K. Banerjee
    ESD Forum, Berlin, Dec. 1-2, 2009
  101. Impact of Strain Engineering and Channel Orientation on the ESD Performance of Nanometer Scale CMOS Devices
    J. Lu, C. Duvvury, H. Gossner and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), Baltimore, Dec. 6-9, 2009
  102. Compact AC Modeling and Analysis of Cu, W, and CNT based Through-Silicon Vias (TSVs) in 3-D ICs
    C. Xu, H. Li, R. Suaya, K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), Baltimore, Dec. 6-9, 2009
  103. Single wall carbon nanotube-Aptamer Based Biosensors
    S. H. Varghese, Y. Nakajima, Y. Yoshida, T. Maekawa, T. Hanajiri, K. Banerjee, D. S. Kumar
    7 th International Symposium on Bioscience and Nanotechnology, Tokyo, Japan, December 20-21, 2009.
  104. Aging-Resilient Design of Pipelined Architectures using Novel Detection and Correction Circuits
    H. Dadgour and K. Banerjee
    Design and Test in Europe (DATE), Dresden, Germany March 8-12, pp. 244-249, 2010.
  105. Efficient 3D High-frequency Impedance Extraction for General Interconnects and Inductors Above a Layered Substrate
    N. Srivastava, R. Suaya and K. Banerjee
    Design and Test in Europe (DATE), Dresden, Germany March 8-12, pp. 459-464, 2010.
  106. A Built-in Aging Detection and Compensation Technique for Improving Reliability of Nanoscale CMOS Designs
    H. Dadgour and K. Banerjee
    IEEE International Reliability Physics Symposium (IRPS), May 2-6, Anaheim, CA, pp. 822-825, 2010.
  107. AC Conductance Modeling and Analysis of Graphene Nanoribbon Interconnects
    D. Sarkar, C. Xu, H. Li, and K. Banerjee
    in Proceedings 13th IEEE International Interconnect Technology Conference (IITC), San Francisco, CA, June 7-9, pp.1-3, 2010.
  108. An Efficient 3D Green’s Function Approach for Fast Impedance Extraction of Interconnects and Spiral Inductors in CMOS RF/Millimeter-wavelength Circuits
    N. Srivastava, R. Suaya and K. Banerjee
    IEEE International Interconnect Technology Conference (IITC), San Francisco, CA, June 7-9, pp. 1-3, 2010.
  109. Design and Analysis of Compact Ultra Energy-Efficient Logic Gates Using Laterally-Actuated Double-Electrode NEMS
    H. F. Dadgour, M. M. Hussain, C. Smith and K. Banerjee
    Design Automation Conference (DAC), Anaheim, CA, June 13-18, 2010, pp. 893-896.
  110. Graphene Based Heterostructure Tunnel-FETs for Low-Voltage/High-Performance ICs
    Y. Khatami, M. Krall, H. Li., C. Xu., K. Banerjee
    in Proceedings 68th Device Research Conference (DRC), Notre Dame, IN, June 21-23, 2010, pp. 65-66.
  111. Compact AC Modeling and Performance Analysis of Through-Silicon Vias (TSVs) in 3-D ICs
    C. Xu, H. Li, R. Suaya and K. Banerjee
    28th Progress In Electromagnetics Research Symposium (PIERS), Cambridge, MA, pp.1-2, 2010
  112. A New Paradigm in the Design of Energy-Efficient Digital Circuits Using Laterally-Actuated Double-Gate NEMS
    H.F. Dadgour, M.M. Hussain and K. Banerjee
    IEEE International Symposium on Low Power Electronics and Design (ISLPED), Austin, TX, August 18-20, pp. 7-12, 2010.
  113. Work-function variation induced fluctuation in bias-temperature-instability characteristics of emerging metal-gate devices and implications for digital design
    S. H. Rasouli, K. Endo, and K. Banerjee
    ACM/IEEE International Conf. on Computer-Aided Design (ICCAD), pp. 714-720, San Jose, CA, Nov. 5-8, 2010.
  114. Compact Modeling and Analysis of Coupling Noise Induced by Through-Si-Vias in 3-D ICs
    C. Xu, R. Suaya and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 6-8, pp. 178-181, 2010.
  115. A Quantitative Inquisition into ESD Sensitivity to Strain in Nanoscale CMOS Protection Devices
    D. Sarkar, S. Thijs, D. Linten, C. Russ, H. Gossner and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 6-8, pp. 808-811, 2010.
  116. Factors Influencing the Synthesis of Monolayer and Bilayer Graphene on Copper using Chemical Vapor Deposition
    Wei Liu, Hong Li, Chuan Xu and Kaustav Banerjee
    38th Conference on the Physics and Chemistry of Surfaces and Interfaces (PCSI-38), San Diego, CA, January 16-20, 2011.
  117. Impact of Scaling on the Performance and Reliability Degradation of Metal-Contacts in NEMS Devices
    H. F. Dadgour, M. M. Hussain, A. Cassell, N. Singh and K. Banerjee
    IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, April 10-14, pp. 280-289, 2011.
  118. Demonstration of Vertical Silicon Nanowire Tunnel Field Effect Transistor with Low Subthreshold Slope < 50mV/decade
    R. Gandhi, Z. X. Chen, N. Singh, K. Banerjee, and S. J. Lee
    International Conference on Materials for Advanced Technologies (ICMAT), Singapore, June 26-July 1, 2011.
  119. Compact Capacitance and Capacitive Coupling-Noise Modeling of Through-Oxide Vias in FDSOI Based Ultra-High Density 3-D ICs
    C. Xu and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 817-820, Washington DC, Dec. 5-7, 2011.
  120. Fast Extraction of High-Frequency Parallel Admittance of Through-Silicon-Vias and their Capacitive Coupling-Noise to Active Regions
    C. Xu, R. Suaya and K. Banerjee
    IEEE International Microwave Symposium, Montréal, Canada, June 17-22, 2012
  121. Fundamental Limitations of Conventional-FET Biosensors: Quantum-Mechanical-Tunneling to the Rescue
    D. Sarkar and K. Banerjee
    Device Research Conference (DRC), pp. 83-84, Penn State University, University Park, PA, June 18-22, 2012.
  122. ESD Characterization of Atomically-Thin Graphene
    H. Li, C. Russ, W. Liu, D. Johnsson, H. Gossner and K. Banerjee
    34th Annual EOS/ESD Symposium, pp. 1-8, Tucson, AZ, September 9-14, 2012.
  123. A Computational Study of Metal-Contacts to Beyond-Graphene 2D Semiconductor Materials
    Jiahao Kang, Deblina Sarkar, Wei Liu, Debdeep Jena and Kaustav Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 407-410, San Francisco, Dec. 10-12, 2012
  124. 2-Dimensional Tunnel Devices and Circuits on Graphene: Opportunities and Challenges
    Jiahao Kang, Wei Cao, Deblina Sarkar, Yasin Khatami, Wei Liu and Kaustav Banerjee
    3rd Berkeley Symposium on Energy Efficient Electronic Systems, Berkeley, CA, Oct 28-29, 2013, pp. 1-2.
  125. High-Performance Few-Layer-MoS2 Field-Effect-Transistor with Record Low Contact-Resistance
    W. Liu, J. Kang, W. Cao, D. Sarkar, Y. Khatami, D. Jena and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), Washington DC, Dec. 9-11, 2013, pp. 499-502.
  126. Computational Study of Interfaces between 2D MoS2 and Surroundings
    Jiahao Kang, Wei Liu and Kaustav Banerjee
    45th IEEE Semiconductor Interface Specialists Conference (SISC), San Diego, CA, December 10-13, 2014.
  127. Graphene Inductors for High-Frequency Applications – Design, Fabrication, Characterization, and Study of Skin Effect
    Xiang Li*, Jiahao Kang*, Xuejun Xie, Wei Liu, Deblina Sarkar, Junfa Mao and Kaustav Banerjee (*equal contributors)
    IEEE International Electron Devices Meeting (IEDM), San Francisco, Dec. 15-17, 2014, pp. 5.4.1–5.4.4.
  128. Performance Evaluation and Design Considerations of 2D Semiconductor based FETs for Sub-10 nm VLSI
    Wei Cao, Jiahao Kang, Deblina Sarkar, Wei Liu, and Kaustav Banerjee
    IEEE International Electron Devices Meeting (IEDM), San Francisco, Dec. 15-17, 2014, pp. 30.5.1–30.5.4.
  129. Designing Band-to-Band Tunneling Field-Effect Transistors with 2D Semiconductors for Next-Generation Low-Power VLSI
    Wei Cao, Junkai Jiang, Jiahao Kang, Deblina Sarkar, Wei Liu, and Kaustav Banerjee
    IEEE International Electron Devices Meeting (IEDM), Washington DC, December 7-9, 2015, pp. 12.3.1-12.3.4.
  130. Prospects of Ultra-thin Nanowire Gated 2D-FETs for Next-Generation CMOS Technology
    Wei Cao, Wei Liu, and Kaustav Banerjee
    IEEE International Electron Devices Meeting (IEDM), San Francisco, December 3-7, 2016, pp. 14.7.1-14.7.4.
  131. Effect of Band-Tails on the Subthreshold Performance of 2D Tunnel-FETs
    Haojun Zhang, Wei Cao, Jiahao Kang, and Kaustav Banerjee
    IEEE International Electron Devices Meeting (IEDM), San Francisco, December 3-7, 2016, pp. 30.3.1-30.3.4.
  132. Characterization of Self-Heating and Current-Carrying Capacity of Intercalation Doped Graphene-Nanoribbon Interconnects
    Junkai Jiang, Jiahao Kang and Kaustav Banerjee
    IEEE International Reliability Physics Symposium (IRPS), Monterey, April 4-6, 2017, pp. 6B.1.1-6B.1.6.