Emerging Nano-Devices & 3D ICs

  1. 3-D Heterogeneous ICs: A Technology for the Next Decade and Beyond
    K. Banerjee, S. J. Souri, P. Kapur and K. C. Saraswat
    5th IEEE Workshop on Signal Propagation on Interconnects, Venice, Italy, May 13-16, 2001 []
  2. RF LDMOS Characterization and Its Compact Modeling
    J. Jang, O. Tornblad, T. Arnborg, Q. Chen, K. Banerjee, Z. Yu and R. W. Dutton
    IEEE/MTT-S International Microwave Symposium, pp. 967-970, Phoenix, AZ, May 20-25, 2001
  3. 3-D Integrable Optoelectronic Devices for Telecommunications ICs
    P. Dainesi, A. M. Ionescu, L. Thevenaz, K. Banerjee, M. J. Declercq, Ph. Robert, Ph. Renaud, Ph. Fluckiger, C. Hibert and G-A. Racine
    IEEE International Solid State Circuits Conference (ISSCC), pp. 360-361, San Francisco, CA, February, 4-6, 2002
  4. Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET (SG-MOSFET) with a Metal Over-Gate-Architecture
    A. M. Ionescu, V. Pott, R. Fritschi, K. Banerjee, M. J. Declercq, Ph. Renaud, C. Hibert, Ph. Fluckiger and G-A. Racine
    IEEE International Symposium on Quality Electronic Design (ISQED), pp. 496-501, San Jose, CA, March 18-21, 2002
  5. SET-based Quantiser Circuit for Digital Communications
    Santanu Mahapatra, Adrian Mihai Ionescu, Kaustav Banerjee and Michel Declercq
    IEE Electronics Letters, Vol. 38, No. 10, pp. 443-445, May 2002
  6. A Quasi-Analytical SET Model for Few Electron Circuit Simulation
    Santanu Mahapatra, Adrian Mihai Ionescu and Kaustav Banerjee
    IEEE Electron Device Letters, Vol. 23, No. 6, pp. 366-368, June 2002
  7. Few Electron Devices: Towards Hybrid CMOS-SET Integrated Circuits
    M. Ionescu, M. J. Declercq, S. Mahapatra, K. Banerjee and J. Gautier
    39th ACM Design Automation Conference (DAC), pp. 88-93, New Orleans, LA, June 10-14, 2002
    INVITED
  8. Quasi-Analytical Modeling of Drain Current and Conductance of Single Electron Transistors with MIB
    S. Mahapatra, A. M. Ionescu and K. Banerjee
    32nd European Solid-State Device Research Conference (ESSDERC), pp. 391-394, Florence, Italy, September 24-26, 2002
  9. Modeling and Analysis of Power Dissipation in Single Electron Logic
    S. Mahapatra, A. M. Ionescu, K. Banerjee and M. J. Declercq
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 323-326, San Francisco, December 8-11, 2002
  10. Teaching Microelectronics in the Silicon ICs Showstopper Zone: A Course on Ultimate Devices and Circuits: Towards Quantum Electronics
    A. M. Ionescu, M. J. Declercq, K. Banerjee and S. Mahapatra
    4th European Workshop on Microelectronics Education (EWME), Baiona, Mancomunidad de Vigo, Spain, May 23-24, 2003 []
  11. A SET Quantizer Circuit Aiming at Digital Communication System
    S. Mahapatra, A. M. Ionescu, K. Banerjee and M. J. Declercq
    IEEE International Symposium on Circuits and Systems (ISCAS), pp. 860-863, Scottsdale, AZ, May 26-29, 2003
  12. A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits
    S. Mahapatra, K. Banerjee, F. Pegeon, and A. M. Ionescu
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 497-502, San Jose, CA, November 9-13, 2003
  13. Nano, Quantum, and Molecular Computing: Are we Ready for the Validation and Test Challenges?
    S. K. Shukla, R. Karri, S. C. Goldstein, F. Brewer, K. Banerjee, and S. Basu
    IEEE International High Level Design Validation and Test Workshop, pp. 3-7, November 12-14, San Francisco, CA, 2003
    INVITED
  14. SETMOS: A Novel True Hybrid SET-CMOS High Current Coulomb Blockade Oscillation Cell for Future Nano-Scale Analog ICs
    S. Mahapatra, V. Pott, S. Ecoffey, A. Schmid, C. Wasshuber, J. W. Tringe, Y. Leblebici, M. Declercq, K. Banerjee and A. M. Ionescu
    IEEE International Electron Devices Meeting (IEDM), pp. 703-706, Washington DC, December 7-10, 2003
  15. A Comprehensive Analytical Capacitance Model of a Two Dimensional Nanodot Array
    A. Basu, S-C. Lin, C. Wasshuber, A. Ionescu and K. Banerjee
    IEEE International Symposium on Quality Electronic Design (ISQED), pp. 259-264, San Jose, CA, March 22-24, 2004
  16. Analytical Modelling of Single Electron Transistor (SET) for Hybrid CMOS-SET Analog IC Design
    Santanu Mahapatra, Vaibhav Vaish, Christoph Wasshuber, Kaustav Banerjee and Adrian Ionescu
    IEEE Transactions on Electron Devices, Vol. 51, No. 11, pp. 1772-1782, Nov. 2004
  17. Emerging Nanoelectronics: Life With and After CMOS, Vol. 1,
    Adrian M. Ionescu and Kaustav Banerjee
    Springer (Kluwer), ISBN: 1-4020-7533-2, 622 pp. (2005)
  18. Emerging Nanoelectronics: Life With and After CMOS, Vol. 2
    Adrian M. Ionescu and Kaustav Banerjee
    Springer (Kluwer), ISBN: 1-4020-7915-X, 340 pp. (2005)
  19. Emerging Nanoelectronics: Life With and After CMOS, Vol. 3
    Adrian M. Ionescu and Kaustav Banerjee
    Springer (Kluwer), ISBN: 1-4020-7916-8, 428 pp. (2005)
  20. Electrothermal Engineering in the Nanometer Era: From Devices and Interconnects to Circuits and Systems
    K. Banerjee, S-C. Lin, and N. Srivastava
    Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 223-230, Yokohama, Japan, Jan. 24-27, 2006
  21. A Thermally-Aware Performance Analysis of Vertically Integrated (3-D) Processor-Memory Hierarchy
    G. Loi, B. Agarwal, N. Srivastava, S-C. Lin, T. Sherwood and K. Banerjee
    ACM Design Automation Conference (DAC), pp. 991-996, San Francisco, CA, July 24-28, 2006
  22. Introspective 3-D Chips
    S. C. Mysore, B. Agrawal, N. Srivastava, S-C. Lin, K. Banerjee and T. Sherwood
    International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pp. 264-273, San Jose, CA, Oct. 25-25, 2006
    IEEE MICRO Top Pick
  23. Power and Thermal Challenges for 65 nm and Below
    K. Banerjee, P. Coteus and V. De
    IEEE International Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 5-9, 2006
    INVITED TUTORIAL
  24. 3D-Integration for Introspection
    Shashidhar Mysore, Banit Agrawal, Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee and Timothy Sherwood
    IEEE Micro: Micro's Top Picks from Computer Architecture Conferences (IEEE Micro - top pick), pp. 77-83, January-February 2007
  25. A Statistical Framework for Estimation of Full-Chip Leakage-Power Distribution under Parameter Variations
    Hamed Dadgour, Sheng-Chih Lin and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 54, No. 11, pp. 2930-2945, Nov. 2007
  26. A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part I: Electrothermal Couplings and Full-Chip Package Thermal Model
    Sheng-Chih Lin, Greg Chrysler, Ravi Mahajan, Vivek De and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 54, No. 12, pp. 3342-3350, 2007
  27. A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part II: Implementation and Implications for Power Estimation and Thermal Management
    Sheng-Chih Lin, Greg Chrysler, Ravi Mahajan, Vivek De and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 54, No. 12, pp. 3351-3360, 2007
  28. Modeling and Analysis of Self-Heating in FinFET Devices for Improved Circuit and EOS/ESD Performance
    S. Kolluri, K. Endo, E. Suzuki and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 177-180, Washington DC, Dec. 10-12, 2007
  29. A Fast Semi-numerical Technique for the Solution of the Poisson-Boltzmann Equation in a Cylindrical Nanowire
    A. Ramu, M. P. Anantram and K. Banerjee
    IEEE International Semiconductor Device Research Symposium (ISDRS), pp. 1-2, College Park, MD, December 12-14, 2007
  30. Cool Chips: Opportunities and Implications for Power and Thermal Management
    Sheng-Chih Lin and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Special Issue on Device Technologies and Circuit Techniques for Power Management, Vol. 55, No. 1, pp. 245-255, 2008
    HIGHLIGHTED ON THE JOURNAL COVER
  31. A Design-Specific and Thermally-Aware Methodology for Trading-off Power and Performance in Leakage-Dominant CMOS Technologies
    Sheng-Chih Lin and Kaustav Banerjee
    IEEE Transactions on Very Large Scale Integration Systems, Vol. 16, No. 11, pp. 1488-1498, Nov. 2008
  32. Statistical Modeling of Metal-Gate Work-Function Variability in Emerging Device Technologies and Implications for Circuit Design
    H. Dadgour, V. De and K. Banerjee
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 270-277, San Jose, Nov. 10-13, 2008
    Nominated for the BEST PAPER AWARD
  33. Modeling and Analysis of Grain-Orientation Effects in Emerging Metal-Gate Devices and Implications for SRAM Reliability
    H. Dadgour, K. Endo, V. De and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 705-708, San Francisco, Dec. 15-17, 2008
  34. High-Speed Low-Power FinFET Based Domino Logic
    S. H. Rasouli, H. Koike and K. Banerjee
    14th Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, Jan. 19-22, 2009
  35. CMOS vs. Nano: Comrades or Rivals?
    K. Banerjee
    17th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, CA, Feb 22-24Panel: CMOS vs. Nano: Comrades or Rivals?
    INVITED PANEL
  36. Variability Analysis of FinFET-Based Devices and Circuits Considering Electrical Confinement and Width Quantization
    S.H. Rasouli, K. Endo, and K. Banerjee
    International Conf. on Computer-Aided Design (ICCAD), San Jose, Nov. 2-5, pp. 505-512, 2009
  37. CAD for Nanoelectronics: Earlier the Better
    K. Banerjee
    IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH’08), June 17-18, 2010, Anaheim, CA PANEL: CAD for Nanoelectronic Circuits and Architectures – Are we there yet?
  38. Effect of Grain Orientation on NBTI Variation and Recovery in Emerging Metal-Gate Devices
    Seid Hadi Rasouli and Kaustav Banerjee
    IEEE Electron Device Letters, Vol. 31, No. 8, pp. 794-796, Aug 2010.
  39. Grain-Orientation Induced Work-Function Variation in Nanoscale Metal-Gate Transistors––Part I: Modeling, Analysis, and Experimental Validation
    Hamed F. Dadgour, Kazuhiko Endo, Vivek De, and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 57, No. 10, pp. 2504-2514, 2010.
  40. Grain-Orientation Induced Work-Function Variation in Nanoscale Metal-Gate Transistors––Part II: Implications for Process, Device, and Circuit Design
    Hamed F. Dadgour, Kazuhiko Endo, Vivek De, and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 57, No. 10, pp. 2515-2525, 2010.
  41. A Novel Enhanced Electric-Field Impact-Ionization MOS Transistor
    Deblina Sarkar, Navab Singh and Kaustav Banerjee
    IEEE Electron Device Letters, vol. 31, no. 11, pp. 1175-1177, Nov. 2010.
  42. A Thermal Simulation Process Based on Electrical. Modeling for Complex Interconnect, Packaging and 3DI Structures
    Lijun Jiang, Chuan Xu, Barry J. Rubin, Alan J. Weger, Alina Deutsch, Howard Smith, Alain Caron, and Kaustav Banerjee
    IEEE Trans. Advanced Packaging, Vol. 33, No. 4, pp. 777-786, Nov. 2010.
  43. Design Optimization of FinFET Domino Logic Considering the Width Quantization Property
    Seid Hadi Rasouli, Hamed F. Dadgour, Kazuhiko Endo, Hanpei Koike, and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 57, No. 11, pp. 2934-2943, Nov. 2010.
  44. Work-function variation induced fluctuation in bias-temperature-instability characteristics of emerging metal-gate devices and implications for digital design
    S. H. Rasouli, K. Endo, and K. Banerjee
    ACM/IEEE International Conf. on Computer-Aided Design (ICCAD), pp. 714-720, San Jose, CA, Nov. 5-8, 2010.
  45. Compact AC Modeling and Performance Analysis of Through-Silicon Vias (TSVs) in 3-D ICs
    Chuan Xu, Hong Li, Roberto Suaya and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 57, No. 12, pp. 3405-3417, Dec. 2010.
  46. Compact Modeling and Analysis of Coupling Noise Induced by Through-Si-Vias in 3-D ICs
    C. Xu, R. Suaya and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 6-8, pp. 178-181, 2010.
  47. Vertical Si-Nanowire n-Type Tunneling FETs With Low Subthreshold Swing (≤ 50 mV/decade) at Room Temperature
    Ramanathan Gandhi, Zhixian Chen, Navab Singh, Kaustav Banerjee, and Sungjoo Lee
    IEEE Electron Device Letters, vol. 32, no. 4, pp. 437-439, April 2011
  48. Demonstration of Vertical Silicon Nanowire Tunnel Field Effect Transistor with Low Subthreshold Slope < 50mV/decade
    R. Gandhi, Z. X. Chen, N. Singh, K. Banerjee, and S. J. Lee
    International Conference on Materials for Advanced Technologies (ICMAT), Singapore, June 26-July 1, 2011.
  49. Grain-Orientation Induced Quantum Confinement Variation in FinFETs and Multi-Gate Ultra-Thin Body CMOS Devices and Implications for Digital Design
    Seid Hadi Rasouli, Kazuhiko Endo, Jone F. Chen, Navab Singh and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Special Issue on "Characterization of Nano CMOS Variability by Simulation and Measurements," vol. 58, no. 8, pp. 2282-2292, Aug. 2011.
  50. A Fully Analytical Model for the Series Impedance of Through-Silicon Vias with Consideration of Substrate Effects and Coupling with Horizontal Interconnects
    Chuan Xu, Vassilis Kourkoulos, Roberto Suaya and Kaustav Banerjee
    IEEE Transactions on Electron Devices, vol. 58, no. 10, pp. 3529-3540, Oct. 2011.
  51. A Physical Model for Work-Function Variation in Ultra-Short Channel Metal-Gate MOSFETs
    Seid Hadi Rasouli, Chuan Xu, Navab Singh and Kaustav Banerjee
    IEEE Electron Device Letters, Vol. 32, No. 11, pp. 1507-1509, Nov. 2011.
  52. Vertically Stacked and Independently Controlled Twin-Gate MOSFETs on a Single Si-Nanowire
    Xiang Li, Zhixian Chen, Nansheng Shen, Deblina Sarkar, Navab Singh, Kaustav Banerjee, Guo-Qiang Lo and Dim-Lee Kwong
    IEEE Electron Device Letters, Vol. 32, No. 11, pp. 1492-1494, Nov. 2011.
  53. CMOS Compatible Vertical Silicon Nanowire Gate-All-Around p-type Tunneling FETs with ≤50 mV/decade Subthreshold Swing
    Ramanathan Gandhi, Zhixian Chen, Navab Singh, Kaustav Banerjee and Sungjoo Lee
    IEEE Electron Device Letters, Vol. 32, No. 11, pp. 1504-1506, Nov. 2011.
  54. Compact Modeling and Analysis of Through-Si-Via Induced Electrical Noise Coupling in 3-D ICs
    Chuan Xu, Roberto Suaya and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 58, No. 11, pp. 4024-4034, Nov. 2011
  55. Compact Capacitance and Capacitive Coupling-Noise Modeling of Through-Oxide Vias in FDSOI Based Ultra-High Density 3-D ICs
    C. Xu and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 817-820, Washington DC, Dec. 5-7, 2011.
  56. Some Results Pertaining Electromagnetic Characterization and Model Building for Passive Systems Including TSVs, for 3-D IC’s Applications
    R. Suaya , C. Xu , V Kourkoulos , K Banerjee, Z. Mahmood and L. Daniel
    IEEE Electrical Design of Advanced Packaging & Systems (EDAPS) Symposium, Hangzhou, China, Dec 12-14, 2011.
  57. Proposal for Tunnel-Field-Effect-Transistor as Ultra-Sensitive and Label-Free Biosensors
    Deblina Sarkar and Kaustav Banerjee
    Applied Physics Letters, 100, No. 14, 143108, 2012
  58. Fast Extraction of High-Frequency Parallel Admittance of Through-Silicon-Vias and their Capacitive Coupling-Noise to Active Regions
    C. Xu, R. Suaya and K. Banerjee
    IEEE International Microwave Symposium, Montréal, Canada, June 17-22, 2012
  59. Fundamental Limitations of Conventional-FET Biosensors: Quantum-Mechanical-Tunneling to the Rescue
    D. Sarkar and K. Banerjee
    Device Research Conference (DRC), pp. 83-84, Penn State University, University Park, PA, June 18-22, 2012.
  60. NEMS based Ultra Energy-Efficient Digital ICs: Materials, Device Architectures, Logic Implementation, and Manufacturability
    H. F. Dadgour and K. Banerjee
    Chapter 10 in Microelectronics to Nanoelectronics: Materials, Devices & Manufacturability. Ed: Anupama B. Kaul, CRC Press, ISBN 9781466509542, July 2012.
  61. Some Clarifications on “Compact Modeling and Analysis of Through-Si-Via Induced Electrical Noise Coupling in Three-Dimensional ICs
    Chuan Xu, Roberto Suaya and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 59, No. 10, pp. 2861-2862, 2012
  62. Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs with Multiple Substrates
    Chuan Xu, Navin Srivastava, Roberto Suaya and Kaustav Banerjee
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, No. 11, pp. 1698-1710, 2012.
  63. A Computational Study of Metal-Contacts to Beyond-Graphene 2D Semiconductor Materials
    Jiahao Kang, Deblina Sarkar, Wei Liu, Debdeep Jena and Kaustav Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 407-410, San Francisco, Dec. 10-12, 2012
  64. Physical Modeling of the Capacitance and Capacitive Coupling-Noise of Through-Oxide Vias in FDSOI Based Ultra-High Density 3-D ICs
    Chuan Xu and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 60, No. 1, pp. 123-131, 2013
  65. Tunnel-Field-Effect-Transistor Based Gas-Sensor: Introducing Gas Detection with a Quantum-Mechanical Transducer
    Deblina Sarkar, Harald Gossner, Walter Hansch and Kaustav Banerjee
    Applied Physics Letters, Vol. 102, No. 2, 023110, 2013.
  66. Graphene nanoribbon based negative resistance device for ultra-low voltage digital logic applications
    Yasin Khatami, Jiahao Kang, and Kaustav Banerjee
    Applied Physics Letters, Vol. 102, No.4 , 043114, 2013.
  67. Role of Metal Contacts in Designing High-Performance Monolayer n-Type WSe2 Field-Effect-Transistors
    Wei Liu, Jiahao Kang, Deblina Sarkar, Yasin Khatami, Debdeep Jena and Kaustav Banerjee
    Nano Letters, Vol. 13, no. 5, pp. 1983-1990, 2013.
  68. VLSI Technology and Circuits
    K. Banerjee and S. Ikeda
    in Guide to State-of-the-Art Electron Devices, Ed. J. Burghartz, John Wiley & Sons, Ltd, ISBN: 978-1-1183-4726-3, April 22, 2013.
  69. Impact-Ionization Field-Effect-Transistor Based Biosensors for Ultra-Sensitive Detection of Biomolecules
    Deblina Sarkar, Harald Gossner, Walter Hansch and Kaustav Banerjee
    Applied Physics Letters, Vol. 102, No. 20, 203110, 2013
  70. Graphene and Beyond-Graphene 2D-Crystals for Green Electronics
    (INVITED) K. Banerjee, W. Liu, J. Kang, Y. Khatami and D. Sarkar
    18th Silicon Nanoelectronics Workshop, Kyoto, Japan, June 9-10, 2013, pp. 1-2.
  71. Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability
    Chuan Xu, Seshadri K. Kolluri, Kazuhiko Endo and Kaustav Banerjee
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 7, pp. 1045-1058, 2013.
  72. Proposal for All-Graphene Monolithic Logic Circuits
    Jiahao Kang, Deblina Sarkar, Yasin Khatami and Kaustav Banerjee
    Applied Physics Letters, Vol. 103, No. 8, 083113, 2013.
  73. 2D Electronics: Graphene and Beyond
    (KEYNOTE) W. Cao, J. Kang, W. Liu, Y. Khatami, D. Sarkar and K. Banerjee
    43rd European Solid-State Device Research Conference (ESSDERC), Bucharest, Romania, Sept. 16-20, 2013, pp. 1-8. Slides: []
  74. Prospects of nanoCarbons and Emerging 2D-Crystals for Next-Generation Green Electronics
    (INVITED) K. Banerjee
    Advanced Metallization Conference 2013: 23rd Asian Session, The University of Tokyo, Tokyo, Japan, Oct. 7-10, 2013, pp. 1-2.
  75. 2-Dimensional Tunnel Devices and Circuits on Graphene: Opportunities and Challenges
    Jiahao Kang, Wei Cao, Deblina Sarkar, Yasin Khatami, Wei Liu and Kaustav Banerjee
    3rd Berkeley Symposium on Energy Efficient Electronic Systems, Berkeley, CA, Oct 28-29, 2013, pp. 1-2.
  76. High-Performance Field-Effect-Transistors on Monolayer-WSe2
    (INVITED) W. Liu, W. Cao, J. Kang, and K. Banerjee
    ECS Transactions 58 (7), pp. 281-285, 2013.
  77. Novel Logic Devices based on 2D Crystal Semiconductors: Opportunities and Challenges
    (INVITED) P. Zhao, W-S. Hwang, E-S. Kim, R. Feenstra, G. Gu, J. Kang, K. Banerjee, A. Seabaugh, H. Xing and D. Jena
    IEEE International Electron Devices Meeting (IEDM), Washington DC, Dec. 9-11, 2013, pp. 487-490.
  78. High-Performance Few-Layer-MoS2 Field-Effect-Transistor with Record Low Contact-Resistance
    W. Liu, J. Kang, W. Cao, D. Sarkar, Y. Khatami, D. Jena and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), Washington DC, Dec. 9-11, 2013, pp. 499-502.
  79. On the Electrostatics of Bernal-Stacked Few-Layer Graphene on Surface Passivated Semiconductors
    Yasin Khatami, Hong Li, Wei Liu and Kaustav Banerjee
    IEEE Transactions on Nanotechnology, Vol. 13, No. 1, pp. 94-100, 2014.
  80. High-Performance MoS2 Transistors with Low-Resistance Molybdenum Contacts
    Jiahao Kang, Wei Liu and Kaustav Banerjee
    Applied Physics Letters, Vol. 104, No. 9, 093106, 2014.
  81. Carbon Integrated Electronics
    Hong Li, Yasin Khatami, Deblina Sarkar, Jiahao Kang, Chuan Xu, Wei Liu, and Kaustav Banerjee
    in Intelligent Integrated Systems: Technologies, Devices and Architectures. Ed: S. Deleonibus, Pan Stanford Series on Intelligent Nanosystems, pp. 217-274, April 9, 2014.
  82. MoS2 Field-Effect Transistor for Next-Generation Label-Free Biosensors
    Deblina Sarkar, Wei Liu, Xuejun Xie, Aaron Anselmo, Samir Mitragotri and Kaustav Banerjee
    ACS Nano, Vol. 8, No. 4, pp. 3992-4003, 2014.
  83. Correction to MoS2 Field-Effect Transistor for Next-Generation Label-Free Biosensors
    Deblina Sarkar, Wei Liu, Xuejun Xie, Aaron Anselmo, Samir Mitragotri and Kaustav Banerjee
    ACS Nano, 2014.
  84. Graphene and beyond-graphene 2D crystals for next-generation green electronics
    (INVITED) Jiahao Kang, Wei Cao, Xuejun Xie, Deblina Sarkar, Wei Liu and Kaustav Banerjee
    Proc. SPIE 9083, Micro- and Nanotechnology Sensors, Systems, and Applications VI, 908305, June 5, 2014.
  85. Subthreshold-Swing Physics of Tunnel Field-Effect Transistors
    Wei Cao, Deblina Sarkar, Yasin Khatami, Jiahao Kang, and Kaustav Banerjee
    AIP Advances, 4, 067141, June 2014.
  86. Low-Frequency Noise in Bilayer MoS2 Transistor
    Xuejun Xie, Deblina Sarkar, Wei Liu, Jiahao Kang, Ognian Marinov, M. Jamal Deen and Kaustav Banerjee
    ACS Nano, Vol. 8, No. 6, pp. 5633-5640, 2014.
  87. Computational Study of Metal Contacts to Monolayer Transition-Metal Dichalcogenide Semiconductors
    Jiahao Kang, Wei Liu, Deblina Sarkar, Debdeep Jena and Kaustav Banerjee
    Physical Review X, Vol. 4, No. 3, pp. 031005, 2014.
  88. Can 2D-Nanocrystals Extend the Lifetime of Floating-Gate Transistor Based Nonvolatile Memory?
    Wei Cao, Jiahao Kang, Simone Bertolazzi, Andras Kis and Kaustav Banerjee
    IEEE Transactions on Electron Devices, vol. 61, No. 10, pp.3456-3464, 2014.
  89. 2D Crystal Semiconductors: Intimate Contacts
    Debdeep Jena, Kaustav Banerjee and Grace Huili Xing
    Nature Materials (News & Views), Vol. 13, pp. 1076-1078, Dec. 2014.
  90. A Compact Current–Voltage Model for 2D Semiconductor Based Field-Effect Transistors Considering Interface Traps, Mobility Degradation, and Inefficient Doping Effect
    Wei Cao, Jiahao Kang, Wei Liu and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 61, No. 12, pp. 4282-4290, 2014.
  91. Computational Study of Interfaces between 2D MoS2 and Surroundings
    Jiahao Kang, Wei Liu and Kaustav Banerjee
    45th IEEE Semiconductor Interface Specialists Conference (SISC), San Diego, CA, December 10-13, 2014.
  92. Graphene Inductors for High-Frequency Applications – Design, Fabrication, Characterization, and Study of Skin Effect
    Xiang Li*, Jiahao Kang*, Xuejun Xie, Wei Liu, Deblina Sarkar, Junfa Mao and Kaustav Banerjee (*equal contributors)
    IEEE International Electron Devices Meeting (IEDM), San Francisco, Dec. 15-17, 2014, pp. 5.4.1–5.4.4.
  93. Performance Evaluation and Design Considerations of 2D Semiconductor based FETs for Sub-10 nm VLSI
    Wei Cao, Jiahao Kang, Deblina Sarkar, Wei Liu, and Kaustav Banerjee
    IEEE International Electron Devices Meeting (IEDM), San Francisco, Dec. 15-17, 2014, pp. 30.5.1–30.5.4.
  94. Functionalization of Transition Metal Dichalcogenides with Metallic Nanoparticles: Implications for Doping and Gas-Sensing
    Deblina Sarkar, Xuejun Xie, Jiahao Kang, Haojun Zhang, Wei Liu, Jose Navarrete, Martin Moskovits, and Kaustav Banerjee
    Nano Letters, Vol. 15, no. 5, pp. 2852–2862, 2015.
  95. Impact of Contact on the Operation and Performance of Back-Gated Monolayer MoS2 Field-Effect-Transistors
    Wei Liu, Deblina Sarkar, Jiahao Kang, Wei Cao, and Kaustav Banerjee
    ACS Nano, Vol. 9, No. 8, pp. 7904–7912, 2015.
  96. 2D Crystals and their Heterostructures for Green Electronics
    (INVITED) Kaustav Banerjee
    Proceedings of the 11th Topical Workshop on Heterostructure Microelectronics, Takayama, Japan, Aug 24-26, p. 10-1, 2015.
  97. 2D Crystals for Smart Life
    (INVITED SHORT COURSE) K. Banerjee
    47th International Conference on Solid State Devices and Materials (SSDM), Sapporo, Japan, Sept. 27-30, 2015.
  98. A Subthermionic Tunnel Field-Effect Transistor with an Atomically Thin Channel
    Deblina Sarkar, Xuejun Xie, Wei Liu, Wei Cao, Jiahao Kang, Yongji Gong, Stephan Kraemer, Pulickel M. Ajayan and Kaustav Banerjee
    Nature, Vol. 526, pp. 91-95, 2015.
  99. 2D Semiconductor FETs- Projections and Design for Sub-10 nm VLSI
    Wei Cao, Jiahao Kang, Deblina Sarkar, Wei Liu and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Special Issue to commemorate the 60th anniversary of the IEDM, Vol. 62, No. 11, pp. 3459-3469, 2015.
  100. ATLAS-TFET: Toward Green Transistors and Sensors
    (INVITED) K. Banerjee
    International Workshop on Dielectric Thin Films For Future Electron Devices (IWDTF), Miraikan, Tokyo, Japan, November 2-4, p. 1-4, 2015.
  101. Engineered 2D Nanomaterials–Protein Interfaces for Efficient Sensors
    K. K. Tadi, T. N Narayanan, S. Arepalli, K. Banerjee, S. Viswanathan, D. Liepmann, P. M Ajayan, V. Renugopalakrishnan
    Journal of Materials Research, Cambridge University Press, Vol. 30, No. 23, pp. 3565-3574, 2015.
  102. Electrical Contacts to Two-dimensional Semiconductors
    Adrien Allain, Jiahao Kang, Kaustav Banerjee and Andras Kis
    Nature Materials, Vol. 14, pp. 1195–1205, 2015.
  103. Designing Band-to-Band Tunneling Field-Effect Transistors with 2D Semiconductors for Next-Generation Low-Power VLSI
    Wei Cao, Junkai Jiang, Jiahao Kang, Deblina Sarkar, Wei Liu, and Kaustav Banerjee
    IEEE International Electron Devices Meeting (IEDM), Washington DC, December 7-9, 2015, pp. 12.3.1-12.3.4.
  104. Surface Functionalization of Two-dimensional Metal Chalcogenides by Lewis Acid-Base Chemistry
    S. Lei, X. Wang, B. Li, J. Kang, Y. He, A. George, L. Ge, Y. Gong, P. Dong, Z. Jin, G. Brunetto, W. Chen, Z. Lin, R. Baines, D. S. Galvão, J. Lou, E. Barrera, K. Banerjee, R. Vajtai and P. Ajayan
    Nature Nanotechnology, Vol. 11, No. 5, pp. 465–471, 2016.
  105. Undoped and Catalyst-Free Germanium Nanowires for High-Performance p-type Enhancement-Mode Field-Effect Transistors
    M. Simanullang, G. B. M. Wisna, K. Usami, W. Cao, Y. Kawano, K. Banerjee, S. Oda
    Journal of Materials Chemistry C, Vol. 4, No. 22, pp. 5102-5108, 2016.
  106. Characterization of FeCl3 Intercalation Doped CVD Few-Layer Graphene
    Wei Liu, Jiahao Kang and Kaustav Banerjee
    IEEE Electron Device Letters, Vol. 37, No. 9, pp. 1246 - 1249, Sept. 2016.
  107. Two-Dimensional Van der Waals Materials
    Pulickel Ajayan, Philip Kim, and Kaustav Banerjee
    Physics Today, Vol. 69, No. 9, pp. 38-44, 2016.
  108. An Ultra-Short Channel Monolayer MoS2 FET Defined By the Curvature of a Thin Nanowire
    Wei Cao, Wei Liu, Jiahao Kang, and Kaustav Banerjee
    IEEE Electron Device Letters, Vol. 37, No. 11, pp. 1497-1500, Nov. 2016.
  109. Prospects of Ultra-thin Nanowire Gated 2D-FETs for Next-Generation CMOS Technology
    Wei Cao, Wei Liu, and Kaustav Banerjee
    IEEE International Electron Devices Meeting (IEDM), San Francisco, December 3-7, 2016, pp. 14.7.1-14.7.4.
  110. Effect of Band-Tails on the Subthreshold Performance of 2D Tunnel-FETs
    Haojun Zhang, Wei Cao, Jiahao Kang, and Kaustav Banerjee
    IEEE International Electron Devices Meeting (IEDM), San Francisco, December 3-7, 2016, pp. 30.3.1-30.3.4.
  111. Understanding the Device Physics in Polymer-Based Ionic-Organic Ratchets
    Y. Hu, V. Brus, W. Cao, K. Liao, H. Phan, M. Wang, K. Banerjee, G. C. Bazan, and T-Q. Nguyen
    Advanced Materials, 1606464, 2017. (DOI: 10.1002/adma.201606464)
  112. Intercalation Doped Multilayer-Graphene-Nanoribbons for Next-Generation Interconnects
    Junkai Jiang, Jiahao Kang, Wei Cao, Xuejun Xie, Haojun Zhang, Jae Hwan Chu, Wei Liu, and Kaustav Banerjee
    Nano Letters, Vol. 17, No. 3, pp. 1482-1488, 2017.
  113. 2D/3D Tunnel-FET: Toward Green Transistors and Sensors
    (INVITED) Wei Cao, Jiahao Kang, and Kaustav Banerjee
    ECS Transactions, 77 (5), 185-189, 2017.
  114. Designing Artificial 2D Crystals with Site and Size Controlled Quantum Dots
    Xuejun Xie, Jiahao Kang, Wei Cao, Jae Hwan Chu, Yongji Gong, Pulickel M. Ajayan, and Kaustav Banerjee
    Nature Scientific Reports, Vol. 7, No. 9965, 2017.