Interconnect Modeling & Design

  1. On Thermal Effects in Deep Sub-Micron VLSI Interconnects
    K. Banerjee, A. Mehrotra, A. Sangiovanni-Vincentelli, and C. Hu
    36th ACM Design Automation Conference (DAC), pp. 885-891, New Orleans, LA, June 21-25, 1999 []
  2. Thermal Effects in Deep Sub-micron VLSI Interconnects and Implications for Reliability and Performance
    Kaustav Banerjee
    Electronics Research Laboratory, Memorandum no. UCB/ERL M99/48, September 22, 1999
  3. Thermal Effects in Deep Sub-Micron VLSI Interconnects
    Kaustav Banerjee
    IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 20-22, 2000
    INVITED TUTORIAL
  4. Performance Analysis and Technology of 3-D ICs
    K. C. Saraswat, S. J. Souri, K. Banerjee, P. Kapur
    ACM International Workshop on System Level Interconnect Prediction (SLIP), pp. 85-90, San Diego, CA, April 8-9, 2000
    INVITED
  5. Quantitative Projections of Reliability and Performance for Low-k/Cu Interconnect Systems
    K. Banerjee, A. Mehrotra, W. Hunter, K. C. Saraswat, K. E. Goodson, and S. S. Wong
    38th IEEE Annual International Reliability Physics Symposium Proceedings (IRPS), pp. 354-358, San Jose, CA, April 10- 13, 2000 []
  6. 3-D lCs with Multiple Si Layers: Performance Analysis, and Technology
    K. C. Saraswat, K. Banerjee, A. Joshi. P. Kalavade, S. J. Souri, and V. Subramanian
    197th Meeting of The Electrochemical Society, Toronto, May 14-18, 2000
    INVITED
  7. Multiple Si Layer ICs: Motivation, Performance Analysis, and Design Implications
    S. J. Souri, K. Banerjee, A. Mehrotra, and K. C. Saraswat
    37th ACM Design Automation Conference (DAC), pp. 213-220, June 5-9, Los Angeles, CA, 2000 []
  8. 3-D ICs: Motivation, Performance Analysis, and Technology
    K. C. Saraswat, K. Banerjee, A. R. Joshi, P. Kalavade, P. Kapur, and S. J. Souri
    Proc. 26th European Solid-State Circuits Conference (ESSCIRC ‘2000), Stockholm, Sweden, Sept. 19 - 21, 2000
    INVITED
  9. Thermal Effects in ULSI Interconnects
    K. Banerjee
    Fabless Semiconductor Association (FSA) Design Modeling Workshop, Santa Clara, CA, Oct. 11-12, 2000
    INVITED TUTORIAL
  10. Full Chip Thermal Analysis of Planar (2-D) and Vertically Integrated (3-D) High Performance ICs
    S. Im and K. Banerjee
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 727-730, San Francisco, CA, Dec. 11-13, 2000 []
  11. Interconnect Limits on Gigascale Integration (GSI) in the 21st Century
    Jeffrey A. Davis, Raguraman Venkatesan, Alain Kaloyeros, Michael Beylansky, Shukri J. Souri, Kaustav Banerjee, Krishna C. Saraswat, Arifur Rahman, Rafael Reif, and James. D. Meindl
    Proceedings of the IEEE, Special Issue on Limits of Semiconductor Technology, Vol. 89, No. 3, pp. 305- 324, March 2001 []
    INVITED
  12. Trends for ULSI Interconnections and Their Implications for Thermal, Reliability and Performance Issues
    K. Banerjee
    Seventh International Dielectrics and Conductors for ULSI Multilevel Interconnection Conference (DCMIC), pp. 38-50, Santa Clara, CA, March 5-9, 2001 []
    INVITED
  13. Analysis and Optimization of Thermal Issues in High-Performance VLSI
    K. Banerjee, M. Pedram and A. H. Ajami
    ACM/SIGDA International Symposium on Physical Design (ISPD), pp. 230-237, Sonoma, CA, April 1-4, 2001 []
    INVITED
  14. 3-D ICs: A Novel Chip Design for Improving Deep Submicrometer Interconnect Performance and Systems-on-Chip Integration
    Kaustav Banerjee, Shukri J. Souri, Pawan Kapur, and Krishna C. Saraswat
    Proceedings of the IEEE, Special Issue, Interconnections- Addressing The Next Challenge of IC Technology, Vol. 89, No. 5, pp. 602-633, May 2001 []
    INVITED
  15. Effects of Non-Uniform Substrate Temperature on the Clock Signal Integrity in High Performance Designs
    A. H. Ajami, M. Pedrarn and K. Banerjee
    IEEE Custom Integrated Circuits Conference (CICC), pp. 233-236, San Diego, CA, May 6-9, 2001 []
  16. A Fast Analytical Technique for Estimating the Bounds of On-Chip Clock Wire Inductance
    Y-C. Lu, K. Banerjee, M. Celik and R. W. Dutton
    IEEE Custom Integrated Circuits Conference (CICC), pp. 241-244, San Diego, CA, May 6-9, 2001 []
  17. A New Analytical Thermal Model for Multilevel VLSI Interconnects Incorporating Via Effects
    T-Y Chiang, K. Banerjee and K. C. Saraswat
    IEEE International Interconnect Technology Conference (IITC), pp. 92-94, San Francisco, CA, June 4-6, 2001 []
  18. Non-Uniform Chip-Temperature Dependent Signal Integrity
    A. H. Ajami, K. Banerjee and M. Pedram
    IEEE Symposium on VLSI Technology, pp. 145-146, Kyoto, Japan, June 12-14, 2001 []
  19. Accurate Analysis of On-Chip Inductance Effects and Implications for Optimal Repeater Insertion and Technology Scaling
    K. Banerjee and A. Mehrotra
    IEEE Symposium on VLSI Circuits, pp. 195-198, Kyoto, Japan, June 14-16, 2001 []
  20. Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology RT-Distributed RLC Interconnects
    K. Banerjee and A. Mehrotra
    38th ACM Design Automation Conference (DAC), pp. 798-803, Las Vegas, NV, June 18-22, 2001 []
    BEST PAPER AWARD
  21. Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs
    A. H. Ajami, K. Banerjee, M. Pedram, and L.P.P.P. van Ginneken
    38th ACM Design Automation Conference (DAC), pp. 567-572, Las Vegas, NV, June 18-22, 2001 []
  22. Global (Interconnect) Warming
    Kuastav Banerjee and Amit Mehrotra
    IEEE Circuits and Devices Magazine, Vol. 17, Issue 5, pp. 16-32, September 2001
    INVITED
  23. Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion
    A. H. Ajami, K. Banerjee and M. Pedram
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 44-48, San Jose, CA, November 4-8, 2001 []
  24. Inductance Aware Interconnect Scaling
    Inductance Aware Interconnect Scaling
    IEEE International Symposium on Quality Electronic Design (ISQED), pp. 43-47, San Jose, CA, March 18-21, 2002 []
  25. Power Dissipation Issues in Interconnect Performance Optimization for Sub-180 nm Designs
    K. Banerjee and A. Mehrotra
    IEEE Symposium on VLSI Circuits, pp. 12-15, Honolulu, HI, June 13-15, 2002 []
  26. Analysis of On-Chip Inductance Effects for Distributed RLC Interconnects
    Kaustav Banerjee and Amit Mehrotra
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 8, pp. 904-915, August 2002 []
  27. A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs
    Kaustav Banerjee and Amit Mehrotra
    IEEE Transactions on Electron Devices, Vol. 49, No. 11, pp. 2001-2007, November 2002 []
  28. An Interconnect Scaling Scheme with Constant On-Chip Inductive Effects
    Kaustav Banerjee and Amit Mehrotra
    International Journal of Analog Integrated Circuits and Signal Processing, Vol. 35, pp. 97–105, 2003
  29. Thermal Issues in Designing Nanometer Scale Interconnects
    K. Banerjee
    20th International VLSI Multilevel Interconnection Conference (VMIC), Marina Del Rey, CA, September 22-25, 2003
    INVITED
  30. Nanometer Scale Issues for On-Chip Interconnections
    K. Banerjee
    IUMRS-ICAM, Symposium B-1, Si-LSI-Related Materials, Processes and Characterization Technology, Yokohama, Japan, October 8-13, 2003
    INVITED
  31. 3D ICs DSM Interconnect Performance Modeling and Analysis
    S. Souri, T-Y. Chiang, P. Kapur, K. Banerjee and K. C. Saraswat
    in Interconnect Technology and Design for Gigascale Integration, Editors: Jeffrey A. Davis and James D. Meindl, Springer, ISBN: 1-4020-7606-1, 2003
  32. A Global Interconnect Optimization Scheme for Nanometer Scale VLSI with Implications for Latency, Bandwidth and Power Dissipation
    Man Lung Mui, Kaustav Banerjee and Amit Mehrotra
    IEEE Transactions on Electron Devices, Vol. 51, No. 2, pp. 195-203, February 2004 []
  33. Power Supply Optimization in Sub-130 nm Leakage Dominant Technologies
    Man L Mui, K. Banerjee and A. Mehrotra
    IEEE International Symposium on Quality Electronic Design (ISQED), pp. 409-414, San Jose, CA, March 22-24, 2004 []
  34. A Probabilistic Framework to Estimate Full-Chip Subthreshold Leakage Power Distribution Considering Within-Die and Die-to-Die P-T-V Variations
    S. Zhang, V. Wason and K. Banerjee
    International Symposium on Low Power Electronic Design (ISLPED), pp. 156-161, Newport Beach, CA, August 9-11, 2004 []
  35. Nanometer Scale Interconnect Challenges
    K. Banerjee
    State-Of-The-Art Seminar, 21st International VLSI Multilevel Interconnection Conference (VMIC), Hawaii, Sept. 29-Oct. 2, 2004
  36. A Comparative Scaling Analysis of Metallic and Carbon Nanotube Interconnections for Nanometer Scale VLSI Technologies
    N. Srivastava and K. Banerjee
    Proceedings of the 21st International VLSI Multilevel Interconnect Conference (VMIC), pp. 393-398, Hawaii, Sept. 29-Oct. 2, 2004 []
  37. Interconnect Challenges for Nanoscale Electronic Circuits
    Navin Srivastava and Kaustav Banerjee
    TMS Journal of Materials (JOM), Special Issue on Nanoelectronics, Vol. 56, No. 10, pp. 30-31, October 2004 []
    INVITED
  38. Impact of On-Chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits
    N. Srivastava, X. Qi and K. Banerjee
    IEEE International Symposium on Quality Electronic Design, pp. 346-351, San Jose, CA, March 21-23, (ISQED), 2005, []
  39. Modeling and Analysis of Non-Uniform Substrate Temperature Effects on Global ULSI Interconnects
    Amir H. Ajami, Kaustav Banerjee and Massoud Pedram
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 6, pp. 849-861, 2005 []
  40. A Probabilistic Framework for Power-Optimal Repeater Insertion for Global Interconnects Under Parameter Variations
    V. Wason and K. Banerjee
    International Symposium on Low Power Electronic Design (ISLPED), pp. 131-136, San Diego, CA, August 8-10, 2005 []
    Nominated for the BEST PAPER AWARD
  41. Thermal Modeling of Bonded SOI/3D ICs
    R. V. Joshi, K. Banerjee, T. Smy, K. Guarini, C. T. Chuang, A. Devgan and N. Zamadmar
    Advanced Metallization Conference (AMC), pp. 25-31, Colorado Springs, CO. Sept. 26-29, 2005
  42. Interconnect Modeling and Analysis in the Nanometer Era: Cu and Beyond
    K. Banerjee, S. Im and N. Srivastava
    Advanced Metallization Conference (AMC), Colorado Springs, CO. Sept. 26-29, 2005 []
  43. Performance Analysis of Carbon Nanotube Interconnects for VLSI Applications
    N. Srivastava and K. Banerjee
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 383-390, San Jose, CA, November 6-10, 2005 []
  44. Carbon Nanotube Interconnects: Implications for Performance, Power Dissipation and Thermal Management
    N. Srivastava, R. V. Joshi and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 257-260, Washington DC, Dec. 5-7, 2005
  45. Electrothermal Engineering in the Nanometer Era: From Devices and Interconnects to Circuits and Systems
    K. Banerjee, S-C. Lin, and N. Srivastava
    Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 223-230, Yokohama, Japan, Jan. 24-27, 2006 []
  46. Emerging Interconnect Technologies based on Carbon Nanotubes
    N. Srivastava and K. Banerjee
    IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 27-29, 2006
    INVITED TUTORIAL
  47. Are Carbon Nanotubes the Future of VLSI Interconnections?
    K. Banerjee and N. Srivastava
    ACM Design Automation Conference (DAC), pp. 809-814, San Francisco, CA, July 24-28, 2006
  48. Can Carbon Nanotubes Extend the Lifetime of On-Chip Electrical Interconnections?
    K. Banerjee, S. Im and N. Srivastava
    IEEE Conference on Nano Networks (Nano-Net), Lausanne, Switzerland, Sept. 14-16, 2006
  49. Prospects for Carbon Nanotube Interconnects
    K. Banerjee
    23rd Advanced Metallization Conference (AMC), San Diego, CA, Oct. 16-19, 2006
  50. Modeling and Extraction of Nanometer Scale Interconnects: Challenges and Opportunities
    R. Suaya, R. Escovar, S. Ortiz, K. Banerjee and N. Srivastava
    23rd Advanced Metallization Conference, San Diego, CA, Oct. 16-19, 2006 []
  51. Carbon Nanotubes: An Emerging Alternative for On-Chip VLSI Interconnects
    K. Banerjee
    Future Directions in IC and Package Design Workshop, (FDIP), Scottsdale, AZ, Oct. 22, 2006
  52. Can Carbon Nanotubes Extend the Lifetime of On-Chip VLSI Interconnections?
    K. Banerjee
    IEEE-CPMT Electrical Design of Advanced Packaging Systems (EDAPS), Shanghai, China, December 17-19, 2006
  53. SoC Communication Architectures: Technology, Current Practice, Research and Trends
    K. Banerjee, L. Benini, N. Dutt, K. Lahiri and S. Pasricha
    VLSI Design Conference, Bangalore, India, Jan. 6-10, 2007
    INVITED TUTORIAL
  54. Carbon Nanotube Vias: A Reality Check
    H. Li, N. Srivastava, J-F. Mao, W-Y. Yin and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 207-210, Washington DC, Dec. 10-12, 2007 []
  55. Performance Analysis of Multi-Walled Carbon Nanotube Based Interconnects
    H. Li, W-Y. Yin, J-F. Mao and K. Banerjee
    IEEE International Semiconductor Device Research Symposium (ISDRS), pp. 1-2, College Park, MD, December 12-14, 2007
  56. High-Frequency Mutual Impedance Extraction of VLSI Interconnects in the Presence of a Multi-layer Conducting Substrate
    N. Srivastava, R. Suaya and K. Banerjee
    IEEE Design and Test in Europe (DATE), pp.42-431, Munich, Germany, March 10-14, 2008
  57. High-Frequency Effects in Carbon Nanotube Interconnects
    K. Banerjee
    12th IEEE Workshop on Signal Propagation on Interconnects (SPI), Avignon, Pope's Palace, France, May 12-15, 2008
    KEYNOTE
  58. Circuit Modeling and Performance Analysis of Multi-Walled Carbon Nanotube Interconnects
    Hong Li, Wen-Yan Yin, Kaustav Banerjee, and Jun-Fa Mao
    IEEE Transactions on Electron Devices, Vol. 55, No. 6, pp. 1328-1337, 2008 []
  59. Carbon Nanotube Interconnects for Next Generation ICs
    K. Banerjee
    Summer School on Nanoelectronic Circuits and Tools, EPFL, Lausanne, Switzerland, July 14-18, 2008
    INVITED
  60. Current Status and Future Perspectives of Carbon Nanotube Interconnects
    K. Banerjee, H. Li and N. Srivastava
    IEEE NANO: 8th International Conference on Nanotechnology, pp. 432-436, Arlington, TX, August 18-21, 2008 []
  61. Current Status and Future Perspectives of Carbon Nanotube Interconnects
    K.Banerjee, H. Li and N. Srivastava
    IEEE EMC Symposium, Detroit, MI, August 18-22, 2008. (INVITED)
  62. Graphene Nano-Ribbon (GNR) Interconnects: A Genuine Contender or a Delusive Dream?
    C. Xu, H. Li and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 201-204, San Francisco, Dec. 15-17, 2008 []
  63. High-Frequency Effects in Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design
    H. Li and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 525-528, San Francisco, Dec. 15-17, 2008
  64. Carbon Nanomaterials for Next Generation Interconnects and Passives: Physics, Status and Prospects
    K. Banerjee
    18th Materials for Advanced Metallization Conference (MAM), Grenoble, France, March 8-11
  65. Carbon Nanomaterials for Next Generation Interconnects and Passives: Physics, Status and Prospects
    K. Banerjee
    International Electrostatic Discharge Workshop (IEW), Lake Tahoe, CA, May 18-21, 2009
    KEYNOTE
  66. On the Applicability of Single-Walled Carbon Nanotubes as VLSI Interconnections
    Navin Srivastava, Hong Li, Franz Kreupl, and Kaustav Banerjee
    IEEE Transactions on Nanotechnology, Vol. 8, No. 4, pp. 542-559, July 2009
  67. Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multi-layer Conductive Substrate
    Navin Srivastava, Roberto Suaya and Kaustav Banerjee
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, No. 7, pp. 1047-1060, July 2009 []
  68. Graphene Based Nanomaterials for VLSI Interconnect and Energy-Storage Applications
    K. Banerjee
    ACM/IEEE System Level Interconnect Prediction (SLIP), San Francisco, CA, July 26, 2009
    INVITED PANEL
  69. Modeling, Analysis and Design of Graphene Nano-Ribbon Interconnects
    Chuan Xu, Hong Li, and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol.56, No.8, pp. 1567-1578, Aug 2009 []
  70. Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status and Prospects
    K. Banerjee, H. Li, N. Srivastava and C. Xu
    Progress in Electromagnetics Research Symposium (PIERS), Moscow, Russia, August 18-21, 2009
  71. An Analytical Treatment of High-frequency Impedance Extraction for Interconnects and Inductors in the Presence of a Multi-layer Substrate
    R. Suaya, N. Srivastava and K. Banerjee
    Progress in Electromagnetics Research Symposium (PIERS), Moscow, Russia, August 18-21, 2009
  72. Prospects of Carbon Nanomaterials in VLSI for Interconnections and Energy Storage
    K. Banerjee, H. Li and C. Xu
    31st Annual EOS/ESD Symposium, Anaheim, CA, Aug 30-Sept 4, 2009
  73. Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status and Prospects
    Hong Li, Chuan Xu, Navin Srivastava, and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Special Issue on Compact Interconnect Models for Gigascale Integration, Vol. 56, No. 9, pp. 1799-1821, Sep 2009. []
    INVITED AND HIGHLIGHTED ON THE JOURNAL COVERPAGE
  74. High-Frequency Analysis of Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design
    Hong Li and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 56, No. 10, pp. 2202-2214, Oct 2009 []
  75. Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status and Prospects
    K. Banerjee, H. Li and C. Xu
    International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, Oct. 7-9, 2009
  76. Carbon Based Active and Passive Devices for Next-Generation ICs
    K. Banerjee, H. Dadgour, Y. Khatami, H. Li, C. Xu
    Global COE International Symposium on Silicon Nano Devices in 2030: Prospects by World’s Leading Scientists, Oct. 13-14, Tokyo, 2009
  77. Fast 3-D Thermal Analysis of Complex Interconnect Structures Using Electrical Modeling and Simulation Methodologies
    C. Xu, L. Jiang, S. K. Kolluri, B. J. Rubin, A. Deutsch, H. Smith, K. Banerjee
    International Conf. on Computer-Aided Design (ICCAD), San Jose, Nov. 2-5, pp. 658-665, 2009
  78. Compact AC Modeling and Analysis of Cu, W, and CNT based Through-Silicon Vias (TSVs) in 3-D ICs
    C. Xu, H. Li, R. Suaya, K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), Baltimore, Dec. 6-9, 2009
  79. Carbon Nanomaterial based Interconnects and Passives for Next-Generation ICs
    K. Banerjee, H. Li and C. Xu
    XVth International Workshop on Physics of Semiconductor Devices (IWPSD), New Delhi India, Dec. 15-19, 2009
  80. Efficient 3D High-frequency Impedance Extraction for General Interconnects and Inductors Above a Layered Substrate
    N. Srivastava, R. Suaya and K. Banerjee
    Design and Test in Europe (DATE), Dresden, Germany March 8-12, pp. 459-464, 2010.
  81. Carbon based Nanomaterials as Interconnects and Passives for Next-Generation VLSI and 3-D ICs
    K. Banerjee
    IEEE WMED, Boise, Idaho, April 16, 2010
    INVITED TUTORIAL
  82. Corrections to “Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate”
    Navin Srivastava, Chuan. Xu, Roberto Suaya, and Kaustav Banerjee
    IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 29, No. 5, pp. 849-849, May 2010. []
  83. A Built-in Aging Detection and Compensation Technique for Improving Reliability of Nanoscale CMOS Designs
    H. Dadgour and K. Banerjee
    IEEE International Reliability Physics Symposium (IRPS), May 2-6, Anaheim, CA, pp. 822-825, 2010.
  84. AC Conductance Modeling and Analysis of Graphene Nanoribbon Interconnects
    D. Sarkar, C. Xu, H. Li, and K. Banerjee
    in Proceedings 13th IEEE International Interconnect Technology Conference (IITC), San Francisco, CA, June 7-9, pp.1-3, 2010.
  85. An Efficient 3D Green’s Function Approach for Fast Impedance Extraction of Interconnects and Spiral Inductors in CMOS RF/Millimeter-wavelength Circuits
    N. Srivastava, R. Suaya and K. Banerjee
    IEEE International Interconnect Technology Conference (IITC), San Francisco, CA, June 7-9, pp. 1-3, 2010.
  86. Compact AC Modeling and Performance Analysis of Through-Silicon Vias (TSVs) in 3-D ICs
    C. Xu, H. Li, R. Suaya and K. Banerjee
    28th Progress In Electromagnetics Research Symposium (PIERS), Cambridge, MA, pp.1-2, 2010
  87. Carbon Nanomaterials: The Ideal Interconnect Technology for Next-Generation ICs
    Hong Li, Chuan Xu, and Kaustav Banerjee
    IEEE Design and Test of Computers, Special Issue on Emerging Interconnect Technologies for Gigascale Integration, pp. 20-31, July/August, 2010. []
    INVITED
  88. Accurate Calculations of the High-frequency Impedance Matrix for VLSI Interconnects and Inductors above a Multi-layer Substrate: A VARPRO success story
    N. Srivastava, R. Suaya, V. Pereyra and K. Banerjee
    in Exponential Data Fitting and its Applications, Editors: V. Pereyra and G. Scherer. Bentham Science Publishers, ISBN: 978-1-60805-048-2, 2010.
  89. Prospects of Carbon Nanomaterials for Next-Generation Green Electronics
    K. Banerjee, H. Li, C. Xu, Y. Khatami, H.F. Dadgour, D. Sarkar and W. Liu
    IEEE NANO, Kintex, Seoul, August 17-20, pp. 1-6, 2010.
  90. Compact AC Modeling and Performance Analysis of Through-Silicon Vias (TSVs) in 3-D ICs
    Chuan Xu, Hong Li, Roberto Suaya and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 57, No. 12, pp. 3405-3417, Dec. 2010.
  91. Compact Modeling and Analysis of Coupling Noise Induced by Through-Si-Vias in 3-D ICs
    C. Xu, R. Suaya and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 6-8, pp. 178-181, 2010.
  92. High-Frequency Behavior of Graphene-Based Interconnects—Part I: Impedance Modeling
    Deblina Sarkar, Chuan Xu, Hong Li, and Kaustav Banerjee
    IEEE Transactions on. Electron Devices, vol. 58, no. 3, pp. 843-852, March 2011.
  93. High-Frequency Behavior of Graphene-Based Interconnects—Part II: Impedance Analysis and Implications for Inductor Design
    Deblina Sarkar, Chuan Xu, Hong Li, and Kaustav Banerjee
    IEEE Transactions on Electron Devices, vol. 58, no. 3, pp. 853-859, March 2011.
  94. Carbon Nanotube Vias: Does Ballistic Electron-Phonon Transport Imply Improved Performance and Reliability?
    Hong Li, Navin Srivastava, Jun-Fa Mao, Wen-Yan Yin and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 58, no. 8, pp. 2689-2701, Aug. 2011.
  95. A Fully Analytical Model for the Series Impedance of Through-Silicon Vias with Consideration of Substrate Effects and Coupling with Horizontal Interconnects
    Chuan Xu, Vassilis Kourkoulos, Roberto Suaya and Kaustav Banerjee
    IEEE Transactions on Electron Devices, vol. 58, no. 10, pp. 3529-3540, Oct. 2011.
  96. Compact Modeling and Analysis of Through-Si-Via Induced Electrical Noise Coupling in 3-D ICs
    Chuan Xu, Roberto Suaya and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 58, No. 11, pp. 4024-4034, Nov. 2011
  97. Compact Capacitance and Capacitive Coupling-Noise Modeling of Through-Oxide Vias in FDSOI Based Ultra-High Density 3-D ICs
    C. Xu and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 817-820, Washington DC, Dec. 5-7, 2011.
  98. Future of Carbon Nanomaterials as Next-Generation Interconnects and Passives Devices
    Hong Li, Chuan Xu, Deblina Sarkar, Yasin Khatami, Wei Liu and Kaustav Banerjee
    IEEE Electrical Design of Advanced Packaging & Systems (EDAPS) Symposium, Hangzhou, China, Dec 12-14, 2011
  99. Some Results Pertaining Electromagnetic Characterization and Model Building for Passive Systems Including TSVs, for 3-D IC’s Applications
    R. Suaya , C. Xu , V Kourkoulos , K Banerjee, Z. Mahmood and L. Daniel
    IEEE Electrical Design of Advanced Packaging & Systems (EDAPS) Symposium, Hangzhou, China, Dec 12-14, 2011.
  100. Fast Extraction of High-Frequency Parallel Admittance of Through-Silicon-Vias and their Capacitive Coupling-Noise to Active Regions
    C. Xu, R. Suaya and K. Banerjee
    IEEE International Microwave Symposium, Montréal, Canada, June 17-22, 2012
  101. Metal to Multi-Layer Graphene Contact--Part II: Analysis of Contact Resistance
    Yasin Khatami, Hong Li, Chuan Xu, and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 59, No. 9, pp. 2453-2460, 2012.
  102. Metal to Multi-Layer Graphene Contact--Part I: Contact Resistance Modeling
    Yasin Khatami, Hong Li, Chuan Xu, and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 59, No. 9, pp. 2444-2452, 2012.
  103. Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs with Multiple Substrates
    Chuan Xu, Navin Srivastava, Roberto Suaya and Kaustav Banerjee
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, No. 11, pp. 1698-1710, 2012.
  104. Physical Modeling of the Capacitance and Capacitive Coupling-Noise of Through-Oxide Vias in FDSOI Based Ultra-High Density 3-D ICs
    Chuan Xu and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 60, No. 1, pp. 123-131, 2013
  105. Low-Resistivity Long-Length Horizontal Carbon Nanotube Bundles for Interconnect Applications – Part II: Characterization
    Hong Li, Wei Liu, Alan M. Cassell, Franz Kreupl and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 60, No. 9, pp. 2870-2876, 2013.
  106. Low-Resistivity Long-Length Horizontal Carbon Nanotube Bundles for Interconnect Applications – Part I: Process Development
    Hong Li, Wei Liu, Alan M. Cassell, Franz Kreupl and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 60, No. 9, pp. 2862-2869, 2013.
  107. Prospects of nanoCarbons and Emerging 2D-Crystals for Next-Generation Green Electronics
    (INVITED) K. Banerjee
    Advanced Metallization Conference 2013: 23rd Asian Session, The University of Tokyo, Tokyo, Japan, Oct. 7-10, 2013, pp. 1-2.
  108. Carbon Integrated Electronics
    Hong Li, Yasin Khatami, Deblina Sarkar, Jiahao Kang, Chuan Xu, Wei Liu, and Kaustav Banerjee
    in Intelligent Integrated Systems: Technologies, Devices and Architectures. Ed: S. Deleonibus, Pan Stanford Series on Intelligent Nanosystems, pp. 217-274, April 9, 2014.
  109. Graphene and beyond-graphene 2D crystals for next-generation green electronics
    (INVITED) Jiahao Kang, Wei Cao, Xuejun Xie, Deblina Sarkar, Wei Liu and Kaustav Banerjee
    Proc. SPIE 9083, Micro- and Nanotechnology Sensors, Systems, and Applications VI, 908305, June 5, 2014.
  110. Graphene Inductors for High-Frequency Applications – Design, Fabrication, Characterization, and Study of Skin Effect
    Xiang Li*, Jiahao Kang*, Xuejun Xie, Wei Liu, Deblina Sarkar, Junfa Mao and Kaustav Banerjee (*equal contributors)
    IEEE International Electron Devices Meeting (IEDM), San Francisco, Dec. 15-17, 2014, pp. 5.4.1–5.4.4.
  111. 2D Crystals for Smart Life
    (INVITED SHORT COURSE) K. Banerjee
    47th International Conference on Solid State Devices and Materials (SSDM), Sapporo, Japan, Sept. 27-30, 2015.
  112. Characterization of FeCl3 Intercalation Doped CVD Few-Layer Graphene
    Wei Liu, Jiahao Kang and Kaustav Banerjee
    IEEE Electron Device Letters, Vol. 37, No. 9, pp. 1246 - 1249, Sept. 2016.
  113. Intercalation Doped Multilayer-Graphene-Nanoribbons for Next-Generation Interconnects
    Junkai Jiang, Jiahao Kang, Wei Cao, Xuejun Xie, Haojun Zhang, Jae Hwan Chu, Wei Liu, and Kaustav Banerjee
    Nano Letters, Vol. 17, No. 3, pp. 1482-1488, 2017.
  114. Characterization of Self-Heating and Current-Carrying Capacity of Intercalation Doped Graphene-Nanoribbon Interconnects
    Junkai Jiang, Jiahao Kang and Kaustav Banerjee
    IEEE International Reliability Physics Symposium (IRPS), Monterey, April 4-6, 2017, pp. 6B.1.1-6B.1.6.