Publications: Invited Conference Papers/Talks

  1. High Current Effects in Metal Interconnects
    K. Banerjee, A. Amerasekera, G. Dixit, and C. Hu
    Proceedings of the SRC Topical Research Conference on Reliability, Vanderbilt University, Nashville, Oct. 21-22, 1997
    INVITED
  2. Thermal Effects in Interconnects
    W. Hunter, W-Y. Shih and K. Banerjee
    IEEE Annual International Reliability Physics Symposium (IRPS), Reno, NV, March 30 - April 2, 1998
    INVITED TUTORIAL
  3. Thermal Effects in Deep Sub-Micron VLSI Interconnects
    Kaustav Banerjee
    IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 20-22, 2000
    INVITED TUTORIAL
  4. Performance Analysis and Technology of 3-D ICs
    K. C. Saraswat, S. J. Souri, K. Banerjee, P. Kapur
    ACM International Workshop on System Level Interconnect Prediction (SLIP), pp. 85-90, San Diego, CA, April 8-9, 2000
    INVITED
  5. 3-D lCs with Multiple Si Layers: Performance Analysis, and Technology
    K. C. Saraswat, K. Banerjee, A. Joshi. P. Kalavade, S. J. Souri, and V. Subramanian
    197th Meeting of The Electrochemical Society, Toronto, May 14-18, 2000
    INVITED
  6. 3-D ICs: Motivation, Performance Analysis, and Technology
    K. C. Saraswat, K. Banerjee, A. R. Joshi, P. Kalavade, P. Kapur, and S. J. Souri
    Proc. 26th European Solid-State Circuits Conference (ESSCIRC ‘2000), Stockholm, Sweden, Sept. 19 - 21, 2000
    INVITED
  7. Thermal Effects in ULSI Interconnects
    K. Banerjee
    Fabless Semiconductor Association (FSA) Design Modeling Workshop, Santa Clara, CA, Oct. 11-12, 2000
    INVITED TUTORIAL
  8. Trends for ULSI Interconnections and Their Implications for Thermal, Reliability and Performance Issues
    K. Banerjee
    Seventh International Dielectrics and Conductors for ULSI Multilevel Interconnection Conference (DCMIC), pp. 38-50, Santa Clara, CA, March 5-9, 2001 []
    INVITED
  9. Analysis and Optimization of Thermal Issues in High-Performance VLSI
    K. Banerjee, M. Pedram and A. H. Ajami
    ACM/SIGDA International Symposium on Physical Design (ISPD), pp. 230-237, Sonoma, CA, April 1-4, 2001 []
    INVITED
  10. Interconnect Reliability under ESD Conditions: Physics, Models and Design Guidelines
    K. Banerjee
    23rd Annual EOS/ESD Symposium, pp. 191, Portland, Oregon, September 9-13, 2001 []
  11. Few Electron Devices: Towards Hybrid CMOS-SET Integrated Circuits
    M. Ionescu, M. J. Declercq, S. Mahapatra, K. Banerjee and J. Gautier
    39th ACM Design Automation Conference (DAC), pp. 88-93, New Orleans, LA, June 10-14, 2002 []
    INVITED
  12. Thermal Issues in Designing Nanometer Scale Interconnects
    K. Banerjee
    20th International VLSI Multilevel Interconnection Conference (VMIC), Marina Del Rey, CA, September 22-25, 2003
    INVITED
  13. Nanometer Scale Issues for On-Chip Interconnections
    K. Banerjee
    IUMRS-ICAM, Symposium B-1, Si-LSI-Related Materials, Processes and Characterization Technology, Yokohama, Japan, October 8-13, 2003
    INVITED
  14. Nano, Quantum, and Molecular Computing: Are we Ready for the Validation and Test Challenges?
    S. K. Shukla, R. Karri, S. C. Goldstein, F. Brewer, K. Banerjee, and S. Basu
    IEEE International High Level Design Validation and Test Workshop, pp. 3-7, November 12-14, San Francisco, CA, 2003 []
    INVITED
  15. Nanometer Scale Interconnect Challenges
    K. Banerjee
    State-Of-The-Art Seminar, 21st International VLSI Multilevel Interconnection Conference (VMIC), Hawaii, Sept. 29-Oct. 2, 2004
  16. Thermal Modeling of Bonded SOI/3D ICs
    R. V. Joshi, K. Banerjee, T. Smy, K. Guarini, C. T. Chuang, A. Devgan and N. Zamadmar
    Advanced Metallization Conference (AMC), pp. 25-31, Colorado Springs, CO. Sept. 26-29, 2005
  17. Interconnect Modeling and Analysis in the Nanometer Era: Cu and Beyond
    K. Banerjee, S. Im and N. Srivastava
    Advanced Metallization Conference (AMC), Colorado Springs, CO. Sept. 26-29, 2005 []
  18. Electrothermal Engineering in the Nanometer Era: From Devices and Interconnects to Circuits and Systems
    K. Banerjee, S-C. Lin, and N. Srivastava
    Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 223-230, Yokohama, Japan, Jan. 24-27, 2006 []
  19. Emerging Interconnect Technologies based on Carbon Nanotubes
    N. Srivastava and K. Banerjee
    IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 27-29, 2006
    INVITED TUTORIAL
  20. Are Carbon Nanotubes the Future of VLSI Interconnections?
    K. Banerjee and N. Srivastava
    ACM Design Automation Conference (DAC), pp. 809-814, San Francisco, CA, July 24-28, 2006 []
  21. Can Carbon Nanotubes Extend the Lifetime of On-Chip Electrical Interconnections?
    K. Banerjee, S. Im and N. Srivastava
    IEEE Conference on Nano Networks (Nano-Net), Lausanne, Switzerland, Sept. 14-16, 2006
  22. Prospects for Carbon Nanotube Interconnects
    K. Banerjee
    23rd Advanced Metallization Conference (AMC), San Diego, CA, Oct. 16-19, 2006
  23. Modeling and Extraction of Nanometer Scale Interconnects: Challenges and Opportunities
    R. Suaya, R. Escovar, S. Ortiz, K. Banerjee and N. Srivastava
    23rd Advanced Metallization Conference, San Diego, CA, Oct. 16-19, 2006 []
  24. Thermal Dissipation in Multilayer Devices
    R. V. Joshi, K. Banerjee, T. Smy, K. Guarini, C.T. Chuang and N. Zamadmar
    23rd Advanced Metallization Conference, San Diego, CA, Oct. 16-19, 2006
  25. Carbon Nanotubes: An Emerging Alternative for On-Chip VLSI Interconnects
    K. Banerjee
    Future Directions in IC and Package Design Workshop, (FDIP), Scottsdale, AZ, Oct. 22, 2006
  26. What are Carbon Nanotubes?
    K. Banerjee
    ACM SIGDA Newsletter, Vol. 36, No. 21, Nov. 2006
  27. Power and Thermal Challenges for 65 nm and Below
    K. Banerjee, P. Coteus and V. De
    IEEE International Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 5-9, 2006
    INVITED TUTORIAL
  28. Can Carbon Nanotubes Extend the Lifetime of On-Chip VLSI Interconnections?
    K. Banerjee
    IEEE-CPMT Electrical Design of Advanced Packaging Systems (EDAPS), Shanghai, China, December 17-19, 2006
  29. SoC Communication Architectures: Technology, Current Practice, Research and Trends
    K. Banerjee, L. Benini, N. Dutt, K. Lahiri and S. Pasricha
    VLSI Design Conference, Bangalore, India, Jan. 6-10, 2007
    INVITED TUTORIAL
  30. Electrothermal Engineering in the Nanometer Era
    K. Banerjee
    17th ACM Great Lakes Symposium on VLSI (GLSVLSI), Stresa-Lago Maggiore, Italy, March 11-13, 2007
    INVITED TUTORIAL
  31. Power and Thermal Management in the Nanometer Era
    K. Banerjee
    IEEE CPMT EDAPS, Taipei, Taiwan, December 15-17, 2007
  32. High-Frequency Effects in Carbon Nanotube Interconnects
    K. Banerjee
    12th IEEE Workshop on Signal Propagation on Interconnects (SPI), Avignon, Pope's Palace, France, May 12-15, 2008
    KEYNOTE
  33. Hybrid NEMS-CMOS Circuits
    K. Banerjee
    IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH’08), June 12-13, 2008, Anaheim, CA Panel: Non-CMOS NanoElectronics – Will it ever be real?
    INVITED PANEL
  34. Carbon Nanotube Interconnects for Next Generation ICs
    K. Banerjee
    Summer School on Nanoelectronic Circuits and Tools, EPFL, Lausanne, Switzerland, July 14-18, 2008
    INVITED
  35. Current Status and Future Perspectives of Carbon Nanotube Interconnects
    K. Banerjee, H. Li and N. Srivastava
    IEEE NANO: 8th International Conference on Nanotechnology, pp. 432-436, Arlington, TX, August 18-21, 2008 []
  36. Current Status and Future Perspectives of Carbon Nanotube Interconnects
    K.Banerjee, H. Li and N. Srivastava
    IEEE EMC Symposium, Detroit, MI, August 18-22, 2008. (INVITED)
  37. CMOS vs. Nano: Comrades or Rivals?
    K. Banerjee
    17th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, CA, Feb 22-24 Panel: CMOS vs. Nano: Comrades or Rivals?
    INVITED PANEL
  38. Carbon Nanomaterials for Next Generation Interconnects and Passives: Physics, Status and Prospects
    K. Banerjee
    18th Materials for Advanced Metallization Conference (MAM), Grenoble, France, March 8-11
  39. Graphene Based Transistors: Physics, Status and Future Perspectives
    K. Banerjee, Y. Khatami, C. Kshirsagar, S. H. Rasouli
    International Symposium on Physical Design (ISPD), San Diego, CA, March 29-April 1
  40. Carbon Nanomaterials for Next Generation Interconnects and Passives: Physics, Status and Prospects
    K. Banerjee
    International Electrostatic Discharge Workshop (IEW), Lake Tahoe, CA, May 18-21, 2009
    KEYNOTE
  41. Graphene Based Nanomaterials for VLSI Interconnect and Energy-Storage Applications
    K. Banerjee
    ACM/IEEE System Level Interconnect Prediction (SLIP), San Francisco, CA, July 26, 2009
    INVITED PANEL
  42. Prospects of Carbon Nanomaterials in VLSI for Interconnections and Energy Storage
    K. Banerjee, H. Li and C. Xu
    31st Annual EOS/ESD Symposium, Anaheim, CA, Aug 30-Sept 4, 2009
  43. Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status and Prospects
    K. Banerjee, H. Li and C. Xu
    International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, Oct. 7-9, 2009
  44. Carbon Based Active and Passive Devices for Next-Generation ICs
    K. Banerjee, H. Dadgour, Y. Khatami, H. Li, C. Xu
    Global COE International Symposium on Silicon Nano Devices in 2030: Prospects by World’s Leading Scientists, Oct. 13-14, Tokyo, 2009
  45. Green Electronics using Graphene based Nanomaterials
    K. Banerjee
    Emerging Technologies in Solid State Devices Workshop, Baltimore, MD, December 5 - 6, 2009
  46. Carbon Nanomaterial based Interconnects and Passives for Next-Generation ICs
    K. Banerjee, H. Li and C. Xu
    XVth International Workshop on Physics of Semiconductor Devices (IWPSD), New Delhi India, Dec. 15-19, 2009
  47. Carbon Based Active and Passive Devices for Next-Generation ICs
    K. Banerjee, W. Liu, H. Li, Y.Khatami, and C. Xu
    Ultimate Limit of Integration in Silicon (ULIS), Glasgow, Scotland, March 17-19, 2010.
    INVITED--PLENARY
  48. Carbon based Nanomaterials as Interconnects and Passives for Next-Generation VLSI and 3-D ICs
    K. Banerjee
    IEEE WMED, Boise, Idaho, April 16, 2010
    INVITED TUTORIAL
  49. CAD for Nanoelectronics: Earlier the Better
    K. Banerjee
    IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH’08), June 17-18, 2010, Anaheim, CA PANEL: CAD for Nanoelectronic Circuits and Architectures – Are we there yet?
  50. Prospects of Carbon Nanomaterials for Next-Generation Green Electronics
    K. Banerjee, H. Li, C. Xu, Y. Khatami, H.F. Dadgour, D. Sarkar and W. Liu
    IEEE NANO, Kintex, Seoul, August 17-20, pp. 1-6, 2010.
  51. Carbon-Based Green Electronics
    Kaustav Banerjee
    Materials Research Society (MRS) Fall Symposium, Boston, MA, Nov. 29-Dec. 3, 2010. (INVITED)
  52. Carbon Based Green Electronics
    K. Banerjee
    ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU 2011), Santa Barbara, CA, March 31-April 1, 2011.
    KEYNOTE
  53. Future of Carbon Nanomaterials as Next-Generation Interconnects and Passives Devices
    Hong Li, Chuan Xu, Deblina Sarkar, Yasin Khatami, Wei Liu and Kaustav Banerjee
    IEEE Electrical Design of Advanced Packaging & Systems (EDAPS) Symposium, Hangzhou, China, Dec 12-14, 2011
  54. Some Results Pertaining Electromagnetic Characterization and Model Building for Passive Systems Including TSVs, for 3-D IC’s Applications
    R. Suaya , C. Xu , V Kourkoulos , K Banerjee, Z. Mahmood and L. Daniel
    IEEE Electrical Design of Advanced Packaging & Systems (EDAPS) Symposium, Hangzhou, China, Dec 12-14, 2011.
  55. Graphene Based Green Electronics
    K. Banerjee
    IEEE Electrical Design of Advanced Packaging & Systems (EDAPS) Symposium, Hangzhou, China, Dec 12-14, 2011.
    KEYNOTE
  56. Graphene Based Green Electronics
    K. Banerjee
    International Workshop on Physics of Semiconductors (IWPSD), IIT-Kanpur, India, Dec 18-22, 2011.
    INVITED TALK
  57. Graphene and Beyond-Graphene 2D-Crystals for Green Electronics
    (INVITED) K. Banerjee, W. Liu, J. Kang, Y. Khatami and D. Sarkar
    18th Silicon Nanoelectronics Workshop, Kyoto, Japan, June 9-10, 2013, pp. 1-2.
  58. 2D Electronics: Graphene and Beyond
    (KEYNOTE) W. Cao, J. Kang, W. Liu, Y. Khatami, D. Sarkar and K. Banerjee
    43rd European Solid-State Device Research Conference (ESSDERC), Bucharest, Romania, Sept. 16-20, 2013, pp. 1-8. Slides: []
  59. Prospects of Graphene Electrodes in Photovoltaics
    (INVITED) Y. Khatami, W. Liu, J. Kang and K. Banerjee
    Proc. SPIE 8824, Next Generation (Nano) Photonic and Cell Technologies for Solar Energy Conversion IV, 88240T, September 25, 2013, doi:10.1117/12.2026581. []
  60. Prospects of nanoCarbons and Emerging 2D-Crystals for Next-Generation Green Electronics
    (INVITED) K. Banerjee
    Advanced Metallization Conference 2013: 23rd Asian Session, The University of Tokyo, Tokyo, Japan, Oct. 7-10, 2013, pp. 1-2.
  61. Novel Logic Devices based on 2D Crystal Semiconductors: Opportunities and Challenges
    (INVITED) P. Zhao, W-S. Hwang, E-S. Kim, R. Feenstra, G. Gu, J. Kang, K. Banerjee, A. Seabaugh, H. Xing and D. Jena
    IEEE International Electron Devices Meeting (IEDM), Washington DC, Dec. 9-11, 2013, pp. 487-490. []
  62. Graphene and beyond-graphene 2D crystals for next-generation green electronics
    (INVITED) Jiahao Kang, Wei Cao, Xuejun Xie, Deblina Sarkar, Wei Liu and Kaustav Banerjee
    Proc. SPIE 9083, Micro- and Nanotechnology Sensors, Systems, and Applications VI, 908305, June 5, 2014. []
  63. 2D Crystals and their Heterostructures for Green Electronics
    (INVITED) Kaustav Banerjee
    Proceedings of the 11th Topical Workshop on Heterostructure Microelectronics, Takayama, Japan, Aug 24-26, p. 10-1, 2015.
  64. 2D Crystals for Smart Life
    (INVITED SHORT COURSE) K. Banerjee
    47th International Conference on Solid State Devices and Materials (SSDM), Sapporo, Japan, Sept. 27-30, 2015.
  65. ATLAS-TFET: Toward Green Transistors and Sensors
    (INVITED) K. Banerjee
    International Workshop on Dielectric Thin Films For Future Electron Devices (IWDTF), Miraikan, Tokyo, Japan, November 2-4, p. 1-4, 2015.