Publications: Jounal Papers

  1. The Dependence of W-plug Via EM Performance on Via Size
    Huy A. Le, Kaustav Banerjee, and Joe W. McPherson
    Semiconductor Science and Technology, Vol. 11, pp. 858-864, 1996 []
  2. High-Current Failure Model for VLSI Interconnects Under Short-PuIse Stress Conditions
    Kaustav Banerjee, Ajith Amerasekera, Nathan Cheung, and Chenming Hu
    IEEE Electron Device Letters, Vol. 18, No. 9, pp. 405-407, 1997 []
  3. Characterization of Self-Heating in Advanced VLSI Interconnect Lines Based on Thermal Finite Element Simulation
    Sven Rzepka, Kaustav Banerjee, Ekkehard Meusel, and Chenming Hu
    IEEE Transactions on Components, Packaging, and Manufacturing Technology-A, Vol. 21, No. 3, pp. 406-411, 1998 []
  4. Thermal Characteristics of Sub-Micron Vias Studied by Scanning Joule Expansion Microscopy
    Masanobu Igeta, Kaustav Banerjee, Guanghua Wu, Chenming Hu, and Arun Majumdar
    IEEE Electron Device Letters, Vol. 21, No. 5, pp. 224-226, May 2000 []
  5. Interconnect Limits on Gigascale Integration (GSI) in the 21st Century
    Jeffrey A. Davis, Raguraman Venkatesan, Alain Kaloyeros, Michael Beylansky, Shukri J. Souri, Kaustav Banerjee, Krishna C. Saraswat, Arifur Rahman, Rafael Reif, and James. D. Meindl
    Proceedings of the IEEE, Special Issue on Limits of Semiconductor Technology, Vol. 89, No. 3, pp. 305- 324, March 2001 []
    INVITED
  6. 3-D ICs: A Novel Chip Design for Improving Deep Submicrometer Interconnect Performance and Systems-on-Chip Integration
    Kaustav Banerjee, Shukri J. Souri, Pawan Kapur, and Krishna C. Saraswat
    Proceedings of the IEEE, Special Issue, Interconnections- Addressing The Next Challenge of IC Technology, Vol. 89, No. 5, pp. 602-633, May 2001 []
    INVITED
  7. Global (Interconnect) Warming
    Kuastav Banerjee and Amit Mehrotra
    IEEE Circuits and Devices Magazine, Vol. 17, Issue 5, pp. 16-32, September 2001 []
    INVITED
  8. Analytical Thermal Model for Multilevel VLSI Interconnects Incorporating Via Effect
    Ting-Yen Chiang, Kaustav Banerjee and Krishna C. Saraswat
    IEEE Electron Device Letters, Vol. 23, No. 1, pp. 31-33, Jan. 2002 []
  9. SET-based Quantiser Circuit for Digital Communications
    Santanu Mahapatra, Adrian Mihai Ionescu, Kaustav Banerjee and Michel Declercq
    IEE Electronics Letters, Vol. 38, No. 10, pp. 443-445, May 2002 []
  10. A Quasi-Analytical SET Model for Few Electron Circuit Simulation
    Santanu Mahapatra, Adrian Mihai Ionescu and Kaustav Banerjee
    IEEE Electron Device Letters, Vol. 23, No. 6, pp. 366-368, June 2002 []
  11. Analysis of Gate-Bias-Induced Heating Effects in Deep-Submicron ESD Protection Designs
    Kwang-Hoon Oh, Charvaka Duvvury, Kaustav Banerjee and Robert W. Dutton
    IEEE Transactions on Devices, Materials and Reliability. Vol. 2, No. 2, pp. 36-42, June 2002 []
  12. Analysis and Design of Distributed ESD Protection Circuits for High-Speed Mixed-Signal and RF ICs
    Choshu Ito, Kaustav Banerjee and Robert W. Dutton
    IEEE Transactions on Electron Devices, Vol. 49, No. 8, pp. 1444-1454, August 2002 []
  13. Analysis of On-Chip Inductance Effects for Distributed RLC Interconnects
    Kaustav Banerjee and Amit Mehrotra
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 8, pp. 904-915, August 2002 []
  14. A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs
    Kaustav Banerjee and Amit Mehrotra
    IEEE Transactions on Electron Devices, Vol. 49, No. 11, pp. 2001-2007, November 2002 []
  15. Analysis of Nonuniform ESD Current Distribution in Deep Submicron NMOS Transistors
    Kwang-Hoon Oh, Charvaka Duvvury, Kaustav Banerjee and Robert W. Dutton
    IEEE Transactions on Electron Devices, Vol. 49, No. 12, pp. 2171-2182, December 2002 []
  16. Impact of Gate-to-Contact Spacing on ESD Performance of Salicided Deep Submicron NMOS Transistors
    Kwang-Hoon Oh, Charvaka Duvvury, Kaustav Banerjee and Robert W. Dutton
    IEEE Transactions on Electron Devices, Vol. 49, No. 12, pp. 2183-2192, December 2002 []
  17. An Interconnect Scaling Scheme with Constant On-Chip Inductive Effects
    Kaustav Banerjee and Amit Mehrotra
    International Journal of Analog Integrated Circuits and Signal Processing, Vol. 35, pp. 97–105, 2003 []
  18. A Global Interconnect Optimization Scheme for Nanometer Scale VLSI with Implications for Latency, Bandwidth and Power Dissipation
    Man Lung Mui, Kaustav Banerjee and Amit Mehrotra
    IEEE Transactions on Electron Devices, Vol. 51, No. 2, pp. 195-203, February 2004 []
  19. Modeling Techniques and Verification Methodologies for Substrate Coupling Effects in Mixed-Signal System-on-Chip Designs
    Adil Koukab, Kaustav Banerjee and Michel Declercq
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 6, pp. 823-836, 2004 []
  20. Interconnect Challenges for Nanoscale Electronic Circuits
    Navin Srivastava and Kaustav Banerjee
    TMS Journal of Materials (JOM), Special Issue on Nanoelectronics, Vol. 56, No. 10, pp. 30-31, October 2004 []
    INVITED
  21. Analytical Modelling of Single Electron Transistor (SET) for Hybrid CMOS-SET Analog IC Design
    Santanu Mahapatra, Vaibhav Vaish, Christoph Wasshuber, Kaustav Banerjee and Adrian Ionescu
    IEEE Transactions on Electron Devices, Vol. 51, No. 11, pp. 1772-1782, Nov. 2004 []
  22. Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI
    Amir H. Ajami, Kaustav Banerjee and Massoud Pedram
    International Journal of Analog Integrated Circuits and Signal Processing, Vol. 42, No. 3, pp. 277-290, Springer, 2005 []
  23. Mechanisms Leading to Erratic Snapback Behavior in Bipolar Junction Transistors with Base Emitter Shorted
    Amitabh Chatterjee, Ronald D. Schrimpf, Sameer Pendharkar and Kaustav Banerjee
    Journal of Applied Physics, Vol. 97, 084504, April 15, 2005 []
  24. Modeling and Analysis of Non-Uniform Substrate Temperature Effects on Global ULSI Interconnects
    Amir H. Ajami, Kaustav Banerjee and Massoud Pedram
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 6, pp. 849-861, 2005 []
  25. Supply and Power Optimization in Leakage Dominant Technologies
    Man Lung Mui, Kaustav Banerjee and Amit Mehrotra
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 9, pp. 1362-1371, 2005 []
  26. Scaling Analysis of Multilevel Interconnect Temperatures in High Performance ICs
    Sungjun Im, Navin Srivastava, Kaustav Banerjee and Kenneth E. Goodson
    IEEE Transactions on Electron Devices, Vol. 52, No. 12, pp. 2710-2719, 2005 []
  27. 3D-Integration for Introspection
    Shashidhar Mysore, Banit Agrawal, Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee and Timothy Sherwood
    IEEE Micro: Micro's Top Picks from Computer Architecture Conferences (IEEE Micro - top pick), pp. 77-83, January-February 2007 []
  28. A Statistical Framework for Estimation of Full-Chip Leakage-Power Distribution under Parameter Variations
    Hamed Dadgour, Sheng-Chih Lin and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 54, No. 11, pp. 2930-2945, Nov. 2007 []
  29. A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part I: Electrothermal Couplings and Full-Chip Package Thermal Model
    Sheng-Chih Lin, Greg Chrysler, Ravi Mahajan, Vivek De and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 54, No. 12, pp. 3342-3350, 2007 []
  30. A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part II: Implementation and Implications for Power Estimation and Thermal Management
    Sheng-Chih Lin, Greg Chrysler, Ravi Mahajan, Vivek De and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 54, No. 12, pp. 3351-3360, 2007 []
  31. Cool Chips: Opportunities and Implications for Power and Thermal Management
    Sheng-Chih Lin and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Special Issue on Device Technologies and Circuit Techniques for Power Management, Vol. 55, No. 1, pp. 245-255, 2008 []
    HIGHLIGHTED ON THE JOURNAL COVER
  32. Circuit Modeling and Performance Analysis of Multi-Walled Carbon Nanotube Interconnects
    Hong Li, Wen-Yan Yin, Kaustav Banerjee, and Jun-Fa Mao
    IEEE Transactions on Electron Devices, Vol. 55, No. 6, pp. 1328-1337, 2008 []
  33. A Design-Specific and Thermally-Aware Methodology for Trading-off Power and Performance in Leakage-Dominant CMOS Technologies
    Sheng-Chih Lin and Kaustav Banerjee
    IEEE Transactions on Very Large Scale Integration Systems, Vol. 16, No. 11, pp. 1488-1498, Nov. 2008 []
  34. Accurate Intrinsic Gate Capacitance Model for Carbon Nanotube-Array Based FETs Considering Screening Effect
    Chaitanya Kshirsagar, Hong Li, Tom Kopley, and Kaustav Banerjee
    IEEE Electron Device Letters, Vol. 29, No. 12, pp. 1408-1411, Dec. 2008 []
  35. On the Applicability of Single-Walled Carbon Nanotubes as VLSI Interconnections
    Navin Srivastava, Hong Li, Franz Kreupl, and Kaustav Banerjee
    IEEE Transactions on Nanotechnology, Vol. 8, No. 4, pp. 542-559, July 2009 []
  36. Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multi-layer Conductive Substrate
    Navin Srivastava, Roberto Suaya and Kaustav Banerjee
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, No. 7, pp. 1047-1060, July 2009 []
  37. Modeling, Analysis and Design of Graphene Nano-Ribbon Interconnects
    Chuan Xu, Hong Li, and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol.56, No.8, pp. 1567-1578, Aug 2009 []
  38. Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status and Prospects
    Hong Li, Chuan Xu, Navin Srivastava, and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Special Issue on Compact Interconnect Models for Gigascale Integration, Vol. 56, No. 9, pp. 1799-1821, Sep 2009. []
    INVITED AND HIGHLIGHTED ON THE JOURNAL COVERPAGE
  39. High-Frequency Analysis of Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design
    Hong Li and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 56, No. 10, pp. 2202-2214, Oct 2009 []
  40. Steep Subthreshold Slope n- and p-type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits
    Yasin Khatami and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 56, No. 11, pp. 2752-2761, Nov. 2009 []
  41. Hybrid NEMS-CMOS Integrated Circuits: A Novel Strategy for Energy-Efficient Designs
    Hamed Dadgour and Kaustav Banerjee
    IET Transactions on Computers and Digital Techniques—Special Issue on Advances in Nanoelectronics Circuits and Systems, Vol. 3, No. 6, pp. 593-608, Nov. 2009 []
  42. Corrections to “Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate”
    Navin Srivastava, Chuan. Xu, Roberto Suaya, and Kaustav Banerjee
    IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 29, No. 5, pp. 849-849, May 2010. []
  43. Effect of Grain Orientation on NBTI Variation and Recovery in Emerging Metal-Gate Devices
    Seid Hadi Rasouli and Kaustav Banerjee
    IEEE Electron Device Letters, Vol. 31, No. 8, pp. 794-796, Aug 2010. []
  44. Carbon Nanomaterials: The Ideal Interconnect Technology for Next-Generation ICs
    Hong Li, Chuan Xu, and Kaustav Banerjee
    IEEE Design and Test of Computers, Special Issue on Emerging Interconnect Technologies for Gigascale Integration, pp. 20-31, July/August, 2010. []
    INVITED
  45. Grain-Orientation Induced Work-Function Variation in Nanoscale Metal-Gate Transistors––Part I: Modeling, Analysis, and Experimental Validation
    Hamed F. Dadgour, Kazuhiko Endo, Vivek De, and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 57, No. 10, pp. 2504-2514, 2010. []
  46. Grain-Orientation Induced Work-Function Variation in Nanoscale Metal-Gate Transistors––Part II: Implications for Process, Device, and Circuit Design
    Hamed F. Dadgour, Kazuhiko Endo, Vivek De, and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 57, No. 10, pp. 2515-2525, 2010. []
  47. A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-in Dynamic Gates
    Hamed Dadgour and Kaustav Banerjee
    IEEE Transactions on VLSI Systems, Vol. 18, No. 11, pp. 1567-1577, Nov. 2010. []
  48. A Novel Enhanced Electric-Field Impact-Ionization MOS Transistor
    Deblina Sarkar, Navab Singh and Kaustav Banerjee
    IEEE Electron Device Letters, vol. 31, no. 11, pp. 1175-1177, Nov. 2010. []
  49. A Thermal Simulation Process Based on Electrical. Modeling for Complex Interconnect, Packaging and 3DI Structures
    Lijun Jiang, Chuan Xu, Barry J. Rubin, Alan J. Weger, Alina Deutsch, Howard Smith, Alain Caron, and Kaustav Banerjee
    IEEE Trans. Advanced Packaging, Vol. 33, No. 4, pp. 777-786, Nov. 2010. []
  50. Design Optimization of FinFET Domino Logic Considering the Width Quantization Property
    Seid Hadi Rasouli, Hamed F. Dadgour, Kazuhiko Endo, Hanpei Koike, and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 57, No. 11, pp. 2934-2943, Nov. 2010. []
  51. Compact AC Modeling and Performance Analysis of Through-Silicon Vias (TSVs) in 3-D ICs
    Chuan Xu, Hong Li, Roberto Suaya and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 57, No. 12, pp. 3405-3417, Dec. 2010. []
  52. Electron-hole Duality During Band-to-Band Tunneling Process in Graphene-Nanoribbon Tunnel-Field-Effect Transistors
    Deblina Sarkar, Michael Krall, and Kaustav Banerjee
    Applied Physics Letters, Vol. 97, No. 26, p. 263109, Dec 27, 2010. []
  53. High-Frequency Behavior of Graphene-Based Interconnects—Part I: Impedance Modeling
    Deblina Sarkar, Chuan Xu, Hong Li, and Kaustav Banerjee
    IEEE Transactions on. Electron Devices, vol. 58, no. 3, pp. 843-852, March 2011. []
  54. High-Frequency Behavior of Graphene-Based Interconnects—Part II: Impedance Analysis and Implications for Inductor Design
    Deblina Sarkar, Chuan Xu, Hong Li, and Kaustav Banerjee
    IEEE Transactions on Electron Devices, vol. 58, no. 3, pp. 853-859, March 2011. []
  55. Vertical Si-Nanowire n-Type Tunneling FETs With Low Subthreshold Swing (≤ 50 mV/decade) at Room Temperature
    Ramanathan Gandhi, Zhixian Chen, Navab Singh, Kaustav Banerjee, and Sungjoo Lee
    IEEE Electron Device Letters, vol. 32, no. 4, pp. 437-439, April 2011 []
  56. Grain-Orientation Induced Quantum Confinement Variation in FinFETs and Multi-Gate Ultra-Thin Body CMOS Devices and Implications for Digital Design
    Seid Hadi Rasouli, Kazuhiko Endo, Jone F. Chen, Navab Singh and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Special Issue on "Characterization of Nano CMOS Variability by Simulation and Measurements," vol. 58, no. 8, pp. 2282-2292, Aug. 2011. []
  57. Carbon Nanotube Vias: Does Ballistic Electron-Phonon Transport Imply Improved Performance and Reliability?
    Hong Li, Navin Srivastava, Jun-Fa Mao, Wen-Yan Yin and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 58, no. 8, pp. 2689-2701, Aug. 2011. []
  58. Metallic-Nanoparticle Assisted Enhanced Band-to-Band Tunneling Current
    Deblina Sarkar and Kaustav Banerjee
    Applied Physics Letters, Vol. 99, No. 13, p. 133116, Sept 26, 2011. []
  59. A Fully Analytical Model for the Series Impedance of Through-Silicon Vias with Consideration of Substrate Effects and Coupling with Horizontal Interconnects
    Chuan Xu, Vassilis Kourkoulos, Roberto Suaya and Kaustav Banerjee
    IEEE Transactions on Electron Devices, vol. 58, no. 10, pp. 3529-3540, Oct. 2011. []
  60. A Physical Model for Work-Function Variation in Ultra-Short Channel Metal-Gate MOSFETs
    Seid Hadi Rasouli, Chuan Xu, Navab Singh and Kaustav Banerjee
    IEEE Electron Device Letters, Vol. 32, No. 11, pp. 1507-1509, Nov. 2011. []
  61. Synthesis of High-Quality Monolayer and Bilayer Graphene on Copper using Chemical Vapor Deposition
    Wei Liu, Hong Li, Chuan Xu, Yasin Khatami and Kaustav Banerjee
    CARBON, Vol. 49, No. 13, pp. 4122-4130, Nov. 2011. []
  62. Vertically Stacked and Independently Controlled Twin-Gate MOSFETs on a Single Si-Nanowire
    Xiang Li, Zhixian Chen, Nansheng Shen, Deblina Sarkar, Navab Singh, Kaustav Banerjee, Guo-Qiang Lo and Dim-Lee Kwong
    IEEE Electron Device Letters, Vol. 32, No. 11, pp. 1492-1494, Nov. 2011. []
  63. CMOS Compatible Vertical Silicon Nanowire Gate-All-Around p-type Tunneling FETs with ≤50 mV/decade Subthreshold Swing
    Ramanathan Gandhi, Zhixian Chen, Navab Singh, Kaustav Banerjee and Sungjoo Lee
    IEEE Electron Device Letters, Vol. 32, No. 11, pp. 1504-1506, Nov. 2011. []
  64. Compact Modeling and Analysis of Through-Si-Via Induced Electrical Noise Coupling in 3-D ICs
    Chuan Xu, Roberto Suaya and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 58, No. 11, pp. 4024-4034, Nov. 2011 []
  65. Proposal for Tunnel-Field-Effect-Transistor as Ultra-Sensitive and Label-Free Biosensors
    Deblina Sarkar and Kaustav Banerjee
    Applied Physics Letters, 100, No. 14, 143108, 2012 []
  66. Top Illuminated Inverted Organic UV Photosensors With Single Layer Graphene Electrodes
    Martin Burkhardt, Wei Liu, Christopher G. Shuttle, Kaustav Banerjee, and Michael L. Chabinyc
    Applied Physics Letters, Vol. 101, 033302, 2012. []
  67. Metal to Multi-Layer Graphene Contact--Part II: Analysis of Contact Resistance
    Yasin Khatami, Hong Li, Chuan Xu, and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 59, No. 9, pp. 2453-2460, 2012. []
  68. Metal to Multi-Layer Graphene Contact--Part I: Contact Resistance Modeling
    Yasin Khatami, Hong Li, Chuan Xu, and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 59, No. 9, pp. 2444-2452, 2012. []
  69. Some Clarifications on “Compact Modeling and Analysis of Through-Si-Via Induced Electrical Noise Coupling in Three-Dimensional ICs
    Chuan Xu, Roberto Suaya and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 59, No. 10, pp. 2861-2862, 2012 []
  70. Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs with Multiple Substrates
    Chuan Xu, Navin Srivastava, Roberto Suaya and Kaustav Banerjee
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, No. 11, pp. 1698-1710, 2012. []
  71. Physical Modeling of the Capacitance and Capacitive Coupling-Noise of Through-Oxide Vias in FDSOI Based Ultra-High Density 3-D ICs
    Chuan Xu and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 60, No. 1, pp. 123-131, 2013 []
  72. Tunnel-Field-Effect-Transistor Based Gas-Sensor: Introducing Gas Detection with a Quantum-Mechanical Transducer
    Deblina Sarkar, Harald Gossner, Walter Hansch and Kaustav Banerjee
    Applied Physics Letters, Vol. 102, No. 2, 023110, 2013. []
  73. Graphene nanoribbon based negative resistance device for ultra-low voltage digital logic applications
    Yasin Khatami, Jiahao Kang, and Kaustav Banerjee
    Applied Physics Letters, Vol. 102, No.4 , 043114, 2013. []
  74. Role of Metal Contacts in Designing High-Performance Monolayer n-Type WSe2 Field-Effect-Transistors
    Wei Liu, Jiahao Kang, Deblina Sarkar, Yasin Khatami, Debdeep Jena and Kaustav Banerjee
    Nano Letters, Vol. 13, no. 5, pp. 1983-1990, 2013. []
  75. Impact-Ionization Field-Effect-Transistor Based Biosensors for Ultra-Sensitive Detection of Biomolecules
    Deblina Sarkar, Harald Gossner, Walter Hansch and Kaustav Banerjee
    Applied Physics Letters, Vol. 102, No. 20, 203110, 2013 []
  76. Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability
    Chuan Xu, Seshadri K. Kolluri, Kazuhiko Endo and Kaustav Banerjee
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 7, pp. 1045-1058, 2013. []
  77. Proposal for All-Graphene Monolithic Logic Circuits
    Jiahao Kang, Deblina Sarkar, Yasin Khatami and Kaustav Banerjee
    Applied Physics Letters, Vol. 103, No. 8, 083113, 2013. []
  78. Low-Resistivity Long-Length Horizontal Carbon Nanotube Bundles for Interconnect Applications – Part II: Characterization
    Hong Li, Wei Liu, Alan M. Cassell, Franz Kreupl and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 60, No. 9, pp. 2870-2876, 2013. []
  79. Low-Resistivity Long-Length Horizontal Carbon Nanotube Bundles for Interconnect Applications – Part I: Process Development
    Hong Li, Wei Liu, Alan M. Cassell, Franz Kreupl and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 60, No. 9, pp. 2862-2869, 2013. []
  80. High-Performance Field-Effect-Transistors on Monolayer-WSe2
    (INVITED) W. Liu, W. Cao, J. Kang, and K. Banerjee
    ECS Transactions 58 (7), pp. 281-285, 2013. []
  81. On the Electrostatics of Bernal-Stacked Few-Layer Graphene on Surface Passivated Semiconductors
    Yasin Khatami, Hong Li, Wei Liu and Kaustav Banerjee
    IEEE Transactions on Nanotechnology, Vol. 13, No. 1, pp. 94-100, 2014. []
  82. Controllable and Rapid Synthesis of High-Quality and Large-Area Bernal Stacked Bilayer Graphene using Chemical Vapor Deposition
    Wei Liu, Stephan Krämer, Deblina Sarkar, Hong Li, Pulickel M. Ajayan, and Kaustav Banerjee
    ACS Chemistry of Materials, Vol. 26, No. 2, pp 907-915, 2014. []
  83. High-Performance MoS2 Transistors with Low-Resistance Molybdenum Contacts
    Jiahao Kang, Wei Liu and Kaustav Banerjee
    Applied Physics Letters, Vol. 104, No. 9, 093106, 2014. []
  84. MoS2 Field-Effect Transistor for Next-Generation Label-Free Biosensors
    Deblina Sarkar, Wei Liu, Xuejun Xie, Aaron Anselmo, Samir Mitragotri and Kaustav Banerjee
    ACS Nano, Vol. 8, No. 4, pp. 3992-4003, 2014. []
  85. Correction to MoS2 Field-Effect Transistor for Next-Generation Label-Free Biosensors
    Deblina Sarkar, Wei Liu, Xuejun Xie, Aaron Anselmo, Samir Mitragotri and Kaustav Banerjee
    ACS Nano, 2014. []
  86. On the Electrostatic-Discharge Robustness of Graphene
    Hong Li, Christian C. Russ, Wei Liu, David Johnsson, Harald Gossner and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 61, No. 6, pp. 1920-1928, 2014. []
  87. Subthreshold-Swing Physics of Tunnel Field-Effect Transistors
    Wei Cao, Deblina Sarkar, Yasin Khatami, Jiahao Kang, and Kaustav Banerjee
    AIP Advances, 4, 067141, June 2014. []
  88. Low-Frequency Noise in Bilayer MoS2 Transistor
    Xuejun Xie, Deblina Sarkar, Wei Liu, Jiahao Kang, Ognian Marinov, M. Jamal Deen and Kaustav Banerjee
    ACS Nano, Vol. 8, No. 6, pp. 5633-5640, 2014. []
  89. Computational Study of Metal Contacts to Monolayer Transition-Metal Dichalcogenide Semiconductors
    Jiahao Kang, Wei Liu, Deblina Sarkar, Debdeep Jena and Kaustav Banerjee
    Physical Review X, Vol. 4, No. 3, pp. 031005, 2014. []
  90. Can 2D-Nanocrystals Extend the Lifetime of Floating-Gate Transistor Based Nonvolatile Memory?
    Wei Cao, Jiahao Kang, Simone Bertolazzi, Andras Kis and Kaustav Banerjee
    IEEE Transactions on Electron Devices, vol. 61, No. 10, pp.3456-3464, 2014. []
  91. 2D Crystal Semiconductors: Intimate Contacts
    Debdeep Jena, Kaustav Banerjee and Grace Huili Xing
    Nature Materials (News & Views), Vol. 13, pp. 1076-1078, Dec. 2014. []
  92. A Compact Current–Voltage Model for 2D Semiconductor Based Field-Effect Transistors Considering Interface Traps, Mobility Degradation, and Inefficient Doping Effect
    Wei Cao, Jiahao Kang, Wei Liu and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 61, No. 12, pp. 4282-4290, 2014.
  93. Functionalization of Transition Metal Dichalcogenides with Metallic Nanoparticles: Implications for Doping and Gas-Sensing
    Deblina Sarkar, Xuejun Xie, Jiahao Kang, Haojun Zhang, Wei Liu, Jose Navarrete, Martin Moskovits, and Kaustav Banerjee
    Nano Letters, Vol. 15, no. 5, pp. 2852–2862, 2015.
  94. Impact of Contact on the Operation and Performance of Back-Gated Monolayer MoS2 Field-Effect-Transistors
    Wei Liu, Deblina Sarkar, Jiahao Kang, Wei Cao, and Kaustav Banerjee
    ACS Nano, Vol. 9, No. 8, pp. 7904–7912, 2015.
  95. A Subthermionic Tunnel Field-Effect Transistor with an Atomically Thin Channel
    Deblina Sarkar, Xuejun Xie, Wei Liu, Wei Cao, Jiahao Kang, Yongji Gong, Stephan Kraemer, Pulickel M. Ajayan and Kaustav Banerjee
    Nature, Vol. 526, pp. 91-95, 2015.
  96. 2D Semiconductor FETs- Projections and Design for Sub-10 nm VLSI
    Wei Cao, Jiahao Kang, Deblina Sarkar, Wei Liu and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Special Issue to commemorate the 60th anniversary of the IEDM, Vol. 62, No. 11, pp. 3459-3469, 2015.
  97. Engineered 2D Nanomaterials–Protein Interfaces for Efficient Sensors
    K. K. Tadi, T. N Narayanan, S. Arepalli, K. Banerjee, S. Viswanathan, D. Liepmann, P. M Ajayan, V. Renugopalakrishnan
    Journal of Materials Research, Cambridge University Press, Vol. 30, No. 23, pp. 3565-3574, 2015.
  98. Electrical Contacts to Two-dimensional Semiconductors
    Adrien Allain, Jiahao Kang, Kaustav Banerjee and Andras Kis
    Nature Materials, Vol. 14, pp. 1195–1205, 2015.
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