Robust Design

  1. Characterization of VLSI Circuit Interconnect Heating and Failure under ESD Conditions
    K. Banerjee, A. Amerasekera, and C. Hu
    34th Proceedings of the IEEE Annual International Reliability Physics Symposium (IRPS), pp. 237-245, Dallas, TX, April 30-May 2, 1996
  2. Impact of High Current Stress Conditions on VLSI Interconnect Electromigration Reliability Evaluation
    K. Banerjee, L. Ting, N. Cheung, and C. Hu
    Proceedings of the Thirteenth International VLSI Multilevel Interconnection Conference (VMIC), pp. 289- 294, Santa Clara, CA, June 18-20, 1996
  3. Characterization and Simulation of Self Heating in a Multi Level VLSI Interconnect System under DC and Pulsed Current Conditions
    K. Banerjee, S. Rzepka, A. Amerasekera, and C. Hu
    Proceedings of the SRC TECHCON, Phoenix, AZ, Sept. 1996
  4. Thermal Analysis of the Fusion Limits of Metal Interconnect under Short Duration Current Pulses
    K. Banerjee, S. Rzepka, A. Amerasekera, N. Cheung, and C. Hu
    Final Report, IEEE International Integrated Reliability Workshop (IRW), pp. 98-102, Lake Tahoe, CA, Oct 20-23, 1996
  5. The Dependence of W-plug Via EM Performance on Via Size
    Huy A. Le, Kaustav Banerjee, and Joe W. McPherson
    Semiconductor Science and Technology, Vol. 11, pp. 858-864, 1996
  6. The Effect of Interconnect Scaling and Low-k Dielectric on the Thermal Characteristics of the IC Metal
    K. Banerjee, A. Amerasekera, G. Dixit, and C. Hu
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 65-68, San Francisco, CA, Dec. 8-11, 1996
  7. Failure Mechanisms of Multi Layered Thin Film Metal Interconnects under a High Current Pulse
    K. Banerjee, A. Amerasekera, N. Cheung, and C. Hu
    MRS Spring Symp., San Francisco, CA, March 31-April 4, 1997
  8. Characterization of Contact and Via Failure under Short Duration High Pulsed Current Stress
    K. Banerjee, A. Amerasekera, G. Dixit, N. Cheung, and C. Hu
    35th Proceedings of the IEEE Annual International Reliability Physics Symposium (IRPS), pp. 216-220, Denver, CO, April 8-10, 1997
  9. High-Current Failure Model for VLSI Interconnects Under Short-PuIse Stress Conditions
    Kaustav Banerjee, Ajith Amerasekera, Nathan Cheung, and Chenming Hu
    IEEE Electron Device Letters, Vol. 18, No. 9, pp. 405-407, 1997
  10. Characterization of Self-Heating in Advanced VLSI Interconnect Lines Based on Thermal Finite Element Simulation
    S. Rzepka, K. Banerjee, E. Meusel, and C. Hu
    3rd International Workshop on Thermal Investigations of ICs and Microstructures (THERMINIC), pp. 108-113, Cannes / Cote d'Azur, France, Sept. 21-23, 1997
  11. High Current Effects in Metal Interconnects
    K. Banerjee, A. Amerasekera, G. Dixit, and C. Hu
    Proceedings of the SRC Topical Research Conference on Reliability, Vanderbilt University, Nashville, Oct. 21-22, 1997
    INVITED
  12. Temperature and Current Effects on Small-Geometry-Contact Resistance
    K. Banerjee, A. Amerasekera, G. Dixit, and C. Hu
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 115 -118, Washington DC, Dec. 7-10, 1997
  13. Characterization of Self-Heating in Advanced VLSI Interconnect Lines Based on Thermal Finite Element Simulation
    Sven Rzepka, Kaustav Banerjee, Ekkehard Meusel, and Chenming Hu
    IEEE Transactions on Components, Packaging, and Manufacturing Technology-A, Vol. 21, No. 3, pp. 406-411, 1998
  14. Thermal Effects in Interconnects
    W. Hunter, W-Y. Shih and K. Banerjee
    IEEE Annual International Reliability Physics Symposium (IRPS), Reno, NV, March 30 - April 2, 1998
    INVITED TUTORIAL
  15. High Current Effects in Silicide films for Sub-0.25 micron VLSI Technologies
    K. Banerjee, A. Amerasekera, J. A. Kittl, and C. Hu
    36th Proceedings of the IEEE Annual International Reliability Physics Symposium (IRPS), pp. 284-292, Reno, NV, March 30 – April 2, 1998
  16. A New Quantitative Model for Deep Submicron Contact Resistance
    K. Banerjee, A. Amerasekara, G. Dixit, and C. Hu
    Proceedings of the TECHON, Las Vegas, NV, 1998
  17. Comparison of E and 1/E TDDB Model for Si02 under Long-Term/Low-Field Test Conditions
    J.W. McPherson, V. Reddy, K. Banerjee, and H. Le
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 171-174, San Francisco, CA, Dec. 6-9, 1998
  18. On Thermal Effects in Deep Sub-Micron VLSI Interconnects
    K. Banerjee, A. Mehrotra, A. Sangiovanni-Vincentelli, and C. Hu
    36th ACM Design Automation Conference (DAC), pp. 885-891, New Orleans, LA, June 21-25, 1999
  19. Thermal Effects in Deep Sub-micron VLSI Interconnects and Implications for Reliability and Performance
    Kaustav Banerjee
    Electronics Research Laboratory, Memorandum no. UCB/ERL M99/48, September 22, 1999
  20. Thermal Effects in Deep Sub-Micron VLSI Interconnects
    Kaustav Banerjee
    IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 20-22, 2000
    INVITED TUTORIAL
  21. Process and Layout Dependent Substrate Resistance Modeling for Deep Sub-Micron ESD Protection Devices
    X. Y. Zhang, K. Banerjee, A. Amerasekera, V. Gupta, Z. Yu, and R. W. Dutton
    38th IEEE Annual International Reliability Physics Symposium Proceedings (IRPS), pp. 295-303, San Jose, CA, April 10- 13, 2000
  22. Quantitative Projections of Reliability and Performance for Low-k/Cu Interconnect Systems
    K. Banerjee, A. Mehrotra, W. Hunter, K. C. Saraswat, K. E. Goodson, and S. S. Wong
    38th IEEE Annual International Reliability Physics Symposium Proceedings (IRPS), pp. 354-358, San Jose, CA, April 10- 13, 2000
  23. Microanalysis of VLSI Interconnect Failure Modes under Short-pulse Stress Conditions
    K. Banerjee, D. Y. Kim, A. Amerasekera, C. Hu, S. S. Wong, and K. E. Goodson
    38th IEEE Annual International Reliability Physics Symposium Proceedings (IRPS), pp. 283-288, San Jose, CA, April 10-13, 2000
  24. Sub-Continuum Thermal Simulations of Deep Sub-micron Devices under ESD Conditions
    P. G. Sverdrup, K. Banerjee, C. Dai, W. Shih, R. W. Dutton, and K. E. Goodson
    IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 54-57, Sept. 6-8, Seattle, WA, 2000
  25. Trends for ULSI Interconnections and Their Implications for Thermal, Reliability and Performance Issues
    K. Banerjee
    Seventh International Dielectrics and Conductors for ULSI Multilevel Interconnection Conference (DCMIC), pp. 38-50, Santa Clara, CA, March 5-9, 2001 []
    INVITED
  26. Analysis and Design of ESD Protection Circuits for High-Frequency/RF Applications
    C. Ito, K. Banerjee and R. W. Dutton
    IEEE International Symposium on Quality Electronic Design (ISQED), pp. 117-122, San Jose, CA, March 26-28, 2001
  27. Non-uniform Bipolar Conduction in Single Finger NMOS Transistors and Implications for Deep Submicron ESD Design
    K-H. Oh, C. Duvvury, C. Salling, K. Banerjee, and R. W. Dutton
    39th IEEE Annual International Reliability Physics Symposium (IRPS), pp. 226-234, Orlando, FL, April 30-May 3, 2001
  28. Non-Uniform Chip-Temperature Dependent Signal Integrity
    A. H. Ajami, K. Banerjee and M. Pedram
    IEEE Symposium on VLSI Technology, pp. 145-146, Kyoto, Japan, June 12-14, 2001
  29. Global (Interconnect) Warming
    Kuastav Banerjee and Amit Mehrotra
    IEEE Circuits and Devices Magazine, Vol. 17, Issue 5, pp. 16-32, September 2001
    INVITED
  30. Interconnect Reliability under ESD Conditions: Physics, Models and Design Guidelines
    K. Banerjee
    23rd Annual EOS/ESD Symposium, pp. 191, Portland, Oregon, September 9-13, 2001 []
  31. Analysis and Optimization of Distributed ESD Protection Circuits for High-Speed Mixed Signal and RF Applications
    C. Ito, K. Banerjee and R. W. Dutton
    23rd Annual EOS/ESD Symposium, pp. 355-363, Portland, OR, September 9-13, 2001
  32. Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets
    K. Banerjee and A. Mehrotra
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 158-164, San Jose, CA, November 4-8, 2001
  33. Localized Heating Effects and Scaling of Sub-0.18 Micron CMOS Devices
    E. Pop, K. Banerjee, P. Sverdrup, R. Dutton and K. Goodson
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 677-680, Washington, DC, December 3-5, 2001
  34. Gate Bias Induced Heating Effect and Implications for the Design of Deep Submicron ESD Protection
    K-H. Oh, C. Duvvury, K. Banerjee and R. W. Dutton
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 315-318, Washington, DC, December 3-5, 2001
  35. Modeling and Analysis of Via Hot Spots and Implications for ULSI Interconnect Reliability
    S. Im, K. Banerjee and K. E. Goodson
    40th IEEE Annual International Reliability Physics Symposium (IRPS), pp. 336-345, Dallas, TX, April 8-11, 2002
  36. Investigation of Gate to Contact Spacing Effect on ESD Robustness of Salicided Deep Submicron Single Finger NMOS Transistors
    K-H. Oh, C. Duvvury, K. Banerjee and R. W. Dutton
    40th IEEE Annual International Reliability Physics Symposium (IRPS), pp. 148-155, Dallas, TX, April 8-11, 2002
  37. Analysis of Gate-Bias-Induced Heating Effects in Deep-Submicron ESD Protection Designs
    Kwang-Hoon Oh, Charvaka Duvvury, Kaustav Banerjee and Robert W. Dutton
    IEEE Transactions on Devices, Materials and Reliability. Vol. 2, No. 2, pp. 36-42, June 2002
  38. Analysis and Design of Distributed ESD Protection Circuits for High-Speed Mixed-Signal and RF ICs
    Choshu Ito, Kaustav Banerjee and Robert W. Dutton
    IEEE Transactions on Electron Devices, Vol. 49, No. 8, pp. 1444-1454, August 2002
  39. Analysis and Optimization of Substrate Noise Coupling in Single-Chip RF Transceiver Design
    A. Koukab, K. Banerjee, and M. Declercq
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 309-316, San Jose, CA, November 10-14, 2002
  40. Analysis of Nonuniform ESD Current Distribution in Deep Submicron NMOS Transistors
    Kwang-Hoon Oh, Charvaka Duvvury, Kaustav Banerjee and Robert W. Dutton
    IEEE Transactions on Electron Devices, Vol. 49, No. 12, pp. 2171-2182, December 2002
  41. Impact of Gate-to-Contact Spacing on ESD Performance of Salicided Deep Submicron NMOS Transistors
    Kwang-Hoon Oh, Charvaka Duvvury, Kaustav Banerjee and Robert W. Dutton
    IEEE Transactions on Electron Devices, Vol. 49, No. 12, pp. 2183-2192, December 2002
  42. Non-uniform Conduction Induced Reverse Channel Length Dependence of ESD Reliability for Silicided NMOS Transistors
    K-H. Oh, K. Banerjee, C. Duvvury and R. W. Dutton
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 341-344, San Francisco, December 8-11, 2002
  43. Via Design and Scaling Strategy for Nanometer Scale Interconnect Technologies
    S. Im, K. Banerjee and K. E. Goodson
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 587-590, San Francisco, December 8-11, 2002
  44. Analysis of IR-Drop Scaling with Implications for Deep Submicron P/G Network Designs
    A. H. Ajami, K. Banerjee, A. Mehrotra and M. Pedram
    IEEE International Symposium on Quality Electronic Design (ISQED), pp. 35-40, San Jose, CA, March 24-26, 2003
  45. Modeling of Temperature Dependent Contact Resistance for Analysis of ESD Reliability
    K-H. Oh, J-H. Chun, K. Banerjee, C. Duvvury, and R. W. Dutton
    41st IEEE Annual International Reliability Physics Symposium (IRPS), pp. 249-255, Dallas, TX, March 30-April 4, 2003
  46. Thermal Issues in Designing Nanometer Scale Interconnects
    K. Banerjee
    20th International VLSI Multilevel Interconnection Conference (VMIC), Marina Del Rey, CA, September 22-25, 2003
    INVITED
  47. Nano, Quantum, and Molecular Computing: Are we Ready for the Validation and Test Challenges?
    S. K. Shukla, R. Karri, S. C. Goldstein, F. Brewer, K. Banerjee, and S. Basu
    IEEE International High Level Design Validation and Test Workshop, pp. 3-7, November 12-14, San Francisco, CA, 2003
    INVITED
  48. Impact of Off-state Leakage Current on Electromigration Design Rules for Nanometer Scale CMOS Technologies
    S-C. Lin, A. Basu, A. Keshavarzi, V. De and K. Banerjee
    IEEE Annual International Reliability Physics Symposium (IRPS), pp. 74-78, Phoenix, AZ, April 25-29, 2004
  49. Modeling Techniques and Verification Methodologies for Substrate Coupling Effects in Mixed-Signal System-on-Chip Designs
    Adil Koukab, Kaustav Banerjee and Michel Declercq
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 6, pp. 823-836, 2004
  50. A Probabilistic Framework to Estimate Full-Chip Subthreshold Leakage Power Distribution Considering Within-Die and Die-to-Die P-T-V Variations
    S. Zhang, V. Wason and K. Banerjee
    International Symposium on Low Power Electronic Design (ISLPED), pp. 156-161, Newport Beach, CA, August 9-11, 2004
  51. Nanometer Scale Interconnect Challenges
    K. Banerjee
    State-Of-The-Art Seminar, 21st International VLSI Multilevel Interconnection Conference (VMIC), Hawaii, Sept. 29-Oct. 2, 2004
  52. Interconnect Challenges for Nanoscale Electronic Circuits
    Navin Srivastava and Kaustav Banerjee
    TMS Journal of Materials (JOM), Special Issue on Nanoelectronics, Vol. 56, No. 10, pp. 30-31, October 2004 []
    INVITED
  53. Leakage and Variation Aware Thermal Management of Nanometer Scale ICs
    K. Banerjee, S-C. Lin, and V. Wason
    Proceedings of the IMAPS-Advanced Technology Workshop on Thermal Management, Oct. 25-27, Palo Alto, CA, 2004 []
  54. Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI
    Amir H. Ajami, Kaustav Banerjee and Massoud Pedram
    International Journal of Analog Integrated Circuits and Signal Processing, Vol. 42, No. 3, pp. 277-290, Springer, 2005
  55. Impact of On-Chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits
    N. Srivastava, X. Qi and K. Banerjee
    IEEE International Symposium on Quality Electronic Design, pp. 346-351, San Jose, CA, March 21-23, (ISQED), 2005,
  56. Mechanisms Leading to Erratic Snapback Behavior in Bipolar Junction Transistors with Base Emitter Shorted
    Amitabh Chatterjee, Ronald D. Schrimpf, Sameer Pendharkar and Kaustav Banerjee
    Journal of Applied Physics, Vol. 97, 084504, April 15, 2005
  57. A Probabilistic Framework for Power-Optimal Repeater Insertion for Global Interconnects Under Parameter Variations
    V. Wason and K. Banerjee
    International Symposium on Low Power Electronic Design (ISLPED), pp. 131-136, San Diego, CA, August 8-10, 2005
    Nominated for the BEST PAPER AWARD
  58. Supply and Power Optimization in Leakage Dominant Technologies
    Man Lung Mui, Kaustav Banerjee and Amit Mehrotra
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 9, pp. 1362-1371, 2005
  59. New Physical Insight and Modeling of Second Breakdown (It2) Phenomenon in Advanced ESD Protection Devices
    A. Chatterjee, C. Duvvury and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 203-206, Washington DC, Dec. 5-7, 2005
  60. A Novel Variation-Aware Low-Power Keeper Architecture for Wide Fan-in Dynamic Gates
    H. F. Dadgour, R. V. Joshi and K. Banerjee
    ACM Design Automation Conference (DAC), pp. 977-982, San Francisco, CA, July 24-28, 2006
  61. An Insight into the High Current ESD Behavior of Drain Extended NMOS (DENMOS) Devices in Nanometer Scale CMOS Technologies
    A. Chatterjee, S. Pendharkar, Y-Y. Lin , C. Duvvury and K. Banerjee
    IEEE International Reliability Physics Symposium (IRPS), pp. 608-609, Phoenix, AZ, April 15-19, 2007
  62. A Statistical Framework for Estimation of Full-Chip Leakage-Power Distribution under Parameter Variations
    Hamed Dadgour, Sheng-Chih Lin and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 54, No. 11, pp. 2930-2945, Nov. 2007
  63. A Microscopic Understanding of Nanometer Scale DENMOS Failure Mechanism Under ESD Conditions
    A. Chatterjee, S. Pendharkar, Y-Y. Lin, C. Duvvury and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 181-184, Washington DC, Dec. 10-12, 2007
  64. 3D Device Modeling of Damage Due to Filamentation Under an ESD Event in Nanometer Scale Drain Extended NMOS (DE-NMOS)
    A. Chatterjee, S. Pendharkar, H. Gossner, C. Duvvury and K. Banerjee
    IEEE International Reliability Physics Symposium (IRPS), pp. 639-640, Phoenix, AZ, April 27-May 1, 2008
  65. A Design-Specific and Thermally-Aware Methodology for Trading-off Power and Performance in Leakage-Dominant CMOS Technologies
    Sheng-Chih Lin and Kaustav Banerjee
    IEEE Transactions on Very Large Scale Integration Systems, Vol. 16, No. 11, pp. 1488-1498, Nov. 2008
  66. Statistical Modeling of Metal-Gate Work-Function Variability in Emerging Device Technologies and Implications for Circuit Design
    H. Dadgour, V. De and K. Banerjee
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 270-277, San Jose, Nov. 10-13, 2008
    Nominated for the BEST PAPER AWARD
  67. Scaling and Variability Analysis of CNT-Based NEMS Devices and Circuits with Implications for Process Design
    H. Dadgour, A. M. Cassell and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 529-532, San Francisco, Dec. 15-17, 2008
  68. Modeling and Analysis of Grain-Orientation Effects in Emerging Metal-Gate Devices and Implications for SRAM Reliability
    H. Dadgour, K. Endo, V. De and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 705-708, San Francisco, Dec. 15-17, 2008
  69. Variability Analysis of FinFET-Based Devices and Circuits Considering Electrical Confinement and Width Quantization
    S.H. Rasouli, K. Endo, and K. Banerjee
    International Conf. on Computer-Aided Design (ICCAD), San Jose, Nov. 2-5, pp. 505-512, 2009
  70. Experimental Investigation of ESD Performance for Strained Silicon Nano-Devices
    D. Sarkar, H. Gossner and K. Banerjee
    ESD Forum, Berlin, Dec. 1-2, 2009
  71. Impact of Strain Engineering and Channel Orientation on the ESD Performance of Nanometer Scale CMOS Devices
    J. Lu, C. Duvvury, H. Gossner and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), Baltimore, Dec. 6-9, 2009
  72. Aging-Resilient Design of Pipelined Architectures using Novel Detection and Correction Circuits
    H. Dadgour and K. Banerjee
    Design and Test in Europe (DATE), Dresden, Germany March 8-12, pp. 244-249, 2010.
  73. Effect of Grain Orientation on NBTI Variation and Recovery in Emerging Metal-Gate Devices
    Seid Hadi Rasouli and Kaustav Banerjee
    IEEE Electron Device Letters, Vol. 31, No. 8, pp. 794-796, Aug 2010.
  74. Grain-Orientation Induced Work-Function Variation in Nanoscale Metal-Gate Transistors––Part I: Modeling, Analysis, and Experimental Validation
    Hamed F. Dadgour, Kazuhiko Endo, Vivek De, and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 57, No. 10, pp. 2504-2514, 2010.
  75. Grain-Orientation Induced Work-Function Variation in Nanoscale Metal-Gate Transistors––Part II: Implications for Process, Device, and Circuit Design
    Hamed F. Dadgour, Kazuhiko Endo, Vivek De, and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 57, No. 10, pp. 2515-2525, 2010.
  76. A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-in Dynamic Gates
    Hamed Dadgour and Kaustav Banerjee
    IEEE Transactions on VLSI Systems, Vol. 18, No. 11, pp. 1567-1577, Nov. 2010.
  77. Work-function variation induced fluctuation in bias-temperature-instability characteristics of emerging metal-gate devices and implications for digital design
    S. H. Rasouli, K. Endo, and K. Banerjee
    ACM/IEEE International Conf. on Computer-Aided Design (ICCAD), pp. 714-720, San Jose, CA, Nov. 5-8, 2010.
  78. A Quantitative Inquisition into ESD Sensitivity to Strain in Nanoscale CMOS Protection Devices
    D. Sarkar, S. Thijs, D. Linten, C. Russ, H. Gossner and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 6-8, pp. 808-811, 2010.
  79. Grain-Orientation Induced Quantum Confinement Variation in FinFETs and Multi-Gate Ultra-Thin Body CMOS Devices and Implications for Digital Design
    Seid Hadi Rasouli, Kazuhiko Endo, Jone F. Chen, Navab Singh and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Special Issue on "Characterization of Nano CMOS Variability by Simulation and Measurements," vol. 58, no. 8, pp. 2282-2292, Aug. 2011.
  80. A Physical Model for Work-Function Variation in Ultra-Short Channel Metal-Gate MOSFETs
    Seid Hadi Rasouli, Chuan Xu, Navab Singh and Kaustav Banerjee
    IEEE Electron Device Letters, Vol. 32, No. 11, pp. 1507-1509, Nov. 2011.
  81. NEMS based Ultra Energy-Efficient Digital ICs: Materials, Device Architectures, Logic Implementation, and Manufacturability
    H. F. Dadgour and K. Banerjee
    Chapter 10 in Microelectronics to Nanoelectronics: Materials, Devices & Manufacturability. Ed: Anupama B. Kaul, CRC Press, ISBN 9781466509542, July 2012.
  82. ESD Characterization of Atomically-Thin Graphene
    H. Li, C. Russ, W. Liu, D. Johnsson, H. Gossner and K. Banerjee
    34th Annual EOS/ESD Symposium, pp. 1-8, Tucson, AZ, September 9-14, 2012.
  83. Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability
    Chuan Xu, Seshadri K. Kolluri, Kazuhiko Endo and Kaustav Banerjee
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 7, pp. 1045-1058, 2013.
  84. On the Electrostatic-Discharge Robustness of Graphene
    Hong Li, Christian C. Russ, Wei Liu, David Johnsson, Harald Gossner and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 61, No. 6, pp. 1920-1928, 2014.
  85. Low-Frequency Noise in Bilayer MoS2 Transistor
    Xuejun Xie, Deblina Sarkar, Wei Liu, Jiahao Kang, Ognian Marinov, M. Jamal Deen and Kaustav Banerjee
    ACS Nano, Vol. 8, No. 6, pp. 5633-5640, 2014.
  86. Characterization of Self-Heating and Current-Carrying Capacity of Intercalation Doped Graphene-Nanoribbon Interconnects
    Junkai Jiang, Jiahao Kang and Kaustav Banerjee
    IEEE International Reliability Physics Symposium (IRPS), Monterey, April 4-6, 2017, pp. 6B.1.1-6B.1.6.