Thermal Management

  1. Characterization of VLSI Circuit Interconnect Heating and Failure under ESD Conditions
    K. Banerjee, A. Amerasekera, and C. Hu
    34th Proceedings of the IEEE Annual International Reliability Physics Symposium (IRPS), pp. 237-245, Dallas, TX, April 30-May 2, 1996 []
  2. Characterization and Simulation of Self Heating in a Multi Level VLSI Interconnect System under DC and Pulsed Current Conditions
    K. Banerjee, S. Rzepka, A. Amerasekera, and C. Hu
    Proceedings of the SRC TECHCON, Phoenix, AZ, Sept. 1996
  3. Thermal Analysis of the Fusion Limits of Metal Interconnect under Short Duration Current Pulses
    K. Banerjee, S. Rzepka, A. Amerasekera, N. Cheung, and C. Hu
    Final Report, IEEE International Integrated Reliability Workshop (IRW), pp. 98-102, Lake Tahoe, CA, Oct 20-23, 1996 []
  4. The Effect of Interconnect Scaling and Low-k Dielectric on the Thermal Characteristics of the IC Metal
    K. Banerjee, A. Amerasekera, G. Dixit, and C. Hu
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 65-68, San Francisco, CA, Dec. 8-11, 1996 []
  5. Failure Mechanisms of Multi Layered Thin Film Metal Interconnects under a High Current Pulse
    K. Banerjee, A. Amerasekera, N. Cheung, and C. Hu
    MRS Spring Symp., San Francisco, CA, March 31-April 4, 1997
  6. Characterization of Contact and Via Failure under Short Duration High Pulsed Current Stress
    K. Banerjee, A. Amerasekera, G. Dixit, N. Cheung, and C. Hu
    35th Proceedings of the IEEE Annual International Reliability Physics Symposium (IRPS), pp. 216-220, Denver, CO, April 8-10, 1997 []
  7. High-Current Failure Model for VLSI Interconnects Under Short-PuIse Stress Conditions
    Kaustav Banerjee, Ajith Amerasekera, Nathan Cheung, and Chenming Hu
    IEEE Electron Device Letters, Vol. 18, No. 9, pp. 405-407, 1997 []
  8. Characterization of Self-Heating in Advanced VLSI Interconnect Lines Based on Thermal Finite Element Simulation
    S. Rzepka, K. Banerjee, E. Meusel, and C. Hu
    3rd International Workshop on Thermal Investigations of ICs and Microstructures (THERMINIC), pp. 108-113, Cannes / Cote d'Azur, France, Sept. 21-23, 1997
  9. High Current Effects in Metal Interconnects
    K. Banerjee, A. Amerasekera, G. Dixit, and C. Hu
    Proceedings of the SRC Topical Research Conference on Reliability, Vanderbilt University, Nashville, Oct. 21-22, 1997
    INVITED
  10. Temperature and Current Effects on Small-Geometry-Contact Resistance
    K. Banerjee, A. Amerasekera, G. Dixit, and C. Hu
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 115 -118, Washington DC, Dec. 7-10, 1997 []
  11. Characterization of Self-Heating in Advanced VLSI Interconnect Lines Based on Thermal Finite Element Simulation
    Sven Rzepka, Kaustav Banerjee, Ekkehard Meusel, and Chenming Hu
    IEEE Transactions on Components, Packaging, and Manufacturing Technology-A, Vol. 21, No. 3, pp. 406-411, 1998 []
  12. Thermal Effects in Interconnects
    W. Hunter, W-Y. Shih and K. Banerjee
    IEEE Annual International Reliability Physics Symposium (IRPS), Reno, NV, March 30 - April 2, 1998
    INVITED TUTORIAL
  13. High Current Effects in Silicide films for Sub-0.25 micron VLSI Technologies
    K. Banerjee, A. Amerasekera, J. A. Kittl, and C. Hu
    36th Proceedings of the IEEE Annual International Reliability Physics Symposium (IRPS), pp. 284-292, Reno, NV, March 30 – April 2, 1998 []
  14. A New Quantitative Model for Deep Submicron Contact Resistance
    K. Banerjee, A. Amerasekara, G. Dixit, and C. Hu
    Proceedings of the TECHON, Las Vegas, NV, 1998
  15. Investigation of Self-Heating Phenomenon in Small Geometry Vias Using Scanning Joule-Expansion Microscopy
    K. Banerjee, G. Wu, M. Igeta, A. Amerasekera, A. Majumdar, and C. Hu
    37th IEEE Annual International Reliability Physics Symposium Proceedings (IRPS), pp. 297-302, San Diego, CA, March 23-25, 1999 []
  16. On Thermal Effects in Deep Sub-Micron VLSI Interconnects
    K. Banerjee, A. Mehrotra, A. Sangiovanni-Vincentelli, and C. Hu
    36th ACM Design Automation Conference (DAC), pp. 885-891, New Orleans, LA, June 21-25, 1999 []
  17. Thermal Effects in Deep Sub-micron VLSI Interconnects and Implications for Reliability and Performance
    Kaustav Banerjee
    Electronics Research Laboratory, Memorandum no. UCB/ERL M99/48, September 22, 1999
  18. Thermal Effects in Deep Sub-Micron VLSI Interconnects
    Kaustav Banerjee
    IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 20-22, 2000
    INVITED TUTORIAL
  19. Quantitative Projections of Reliability and Performance for Low-k/Cu Interconnect Systems
    K. Banerjee, A. Mehrotra, W. Hunter, K. C. Saraswat, K. E. Goodson, and S. S. Wong
    38th IEEE Annual International Reliability Physics Symposium Proceedings (IRPS), pp. 354-358, San Jose, CA, April 10- 13, 2000 []
  20. Microanalysis of VLSI Interconnect Failure Modes under Short-pulse Stress Conditions
    K. Banerjee, D. Y. Kim, A. Amerasekera, C. Hu, S. S. Wong, and K. E. Goodson
    38th IEEE Annual International Reliability Physics Symposium Proceedings (IRPS), pp. 283-288, San Jose, CA, April 10-13, 2000 []
  21. Thermal Characteristics of Sub-Micron Vias Studied by Scanning Joule Expansion Microscopy
    Masanobu Igeta, Kaustav Banerjee, Guanghua Wu, Chenming Hu, and Arun Majumdar
    IEEE Electron Device Letters, Vol. 21, No. 5, pp. 224-226, May 2000 []
  22. Multiple Si Layer ICs: Motivation, Performance Analysis, and Design Implications
    S. J. Souri, K. Banerjee, A. Mehrotra, and K. C. Saraswat
    37th ACM Design Automation Conference (DAC), pp. 213-220, June 5-9, Los Angeles, CA, 2000 []
  23. Sub-Continuum Thermal Simulations of Deep Sub-micron Devices under ESD Conditions
    P. G. Sverdrup, K. Banerjee, C. Dai, W. Shih, R. W. Dutton, and K. E. Goodson
    IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 54-57, Sept. 6-8, Seattle, WA, 2000 []
  24. Advanced Electro-Thermal Modeling and Simulation Techniques for Deep Sub-Micron Devices
    P. G. Sverdrup, O. Tornblad, K. Banerjee, D. Yergeau, Z. Yu, R. W. Dutton, and K. E. Goodson
    Proceedings of TECHCON, Phoenix, AZ, Sept. 21-23, 2000
  25. Thermal Effects in ULSI Interconnects
    K. Banerjee
    Fabless Semiconductor Association (FSA) Design Modeling Workshop, Santa Clara, CA, Oct. 11-12, 2000
    INVITED TUTORIAL
  26. Effect of Via Separation and Low-k Dielectric Materials on the Thermal Characteristics of Cu Interconnects
    T-Y. Chiang, K. Banerjee, K. C. Saraswat
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 261-264, San Francisco, CA, Dec. 11-13, 2000 []
  27. Full Chip Thermal Analysis of Planar (2-D) and Vertically Integrated (3-D) High Performance ICs
    S. Im and K. Banerjee
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 727-730, San Francisco, CA, Dec. 11-13, 2000 []
  28. Trends for ULSI Interconnections and Their Implications for Thermal, Reliability and Performance Issues
    K. Banerjee
    Seventh International Dielectrics and Conductors for ULSI Multilevel Interconnection Conference (DCMIC), pp. 38-50, Santa Clara, CA, March 5-9, 2001 []
    INVITED
  29. Analysis and Optimization of Thermal Issues in High-Performance VLSI
    K. Banerjee, M. Pedram and A. H. Ajami
    ACM/SIGDA International Symposium on Physical Design (ISPD), pp. 230-237, Sonoma, CA, April 1-4, 2001 []
    INVITED
  30. 3-D ICs: A Novel Chip Design for Improving Deep Submicrometer Interconnect Performance and Systems-on-Chip Integration
    Kaustav Banerjee, Shukri J. Souri, Pawan Kapur, and Krishna C. Saraswat
    Proceedings of the IEEE, Special Issue, Interconnections- Addressing The Next Challenge of IC Technology, Vol. 89, No. 5, pp. 602-633, May 2001 []
    INVITED
  31. Effects of Non-Uniform Substrate Temperature on the Clock Signal Integrity in High Performance Designs
    A. H. Ajami, M. Pedrarn and K. Banerjee
    IEEE Custom Integrated Circuits Conference (CICC), pp. 233-236, San Diego, CA, May 6-9, 2001 []
  32. A New Analytical Thermal Model for Multilevel VLSI Interconnects Incorporating Via Effects
    T-Y Chiang, K. Banerjee and K. C. Saraswat
    IEEE International Interconnect Technology Conference (IITC), pp. 92-94, San Francisco, CA, June 4-6, 2001 []
  33. Non-Uniform Chip-Temperature Dependent Signal Integrity
    A. H. Ajami, K. Banerjee and M. Pedram
    IEEE Symposium on VLSI Technology, pp. 145-146, Kyoto, Japan, June 12-14, 2001 []
  34. Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs
    A. H. Ajami, K. Banerjee, M. Pedram, and L.P.P.P. van Ginneken
    38th ACM Design Automation Conference (DAC), pp. 567-572, Las Vegas, NV, June 18-22, 2001 []
  35. Global (Interconnect) Warming
    Kuastav Banerjee and Amit Mehrotra
    IEEE Circuits and Devices Magazine, Vol. 17, Issue 5, pp. 16-32, September 2001 []
    INVITED
  36. Interconnect Reliability under ESD Conditions: Physics, Models and Design Guidelines
    K. Banerjee
    23rd Annual EOS/ESD Symposium, pp. 191, Portland, Oregon, September 9-13, 2001 []
  37. Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects
    T-Y. Chiang, K. Banerjee and K. C. Saraswat
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 165-172, San Jose, CA, November 4-8, 2001 []
  38. Coupled Analysis of Electromigration Reliability and Performance in ULS1 Signal Nets
    K. Banerjee and A. Mehrotra
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 158-164, San Jose, CA, November 4-8, 2001 []
  39. Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion
    A. H. Ajami, K. Banerjee and M. Pedram
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 44-48, San Jose, CA, November 4-8, 2001 []
  40. Localized Heating Effects and Scaling of Sub-0.18 Micron CMOS Devices
    E. Pop, K. Banerjee, P. Sverdrup, R. Dutton and K. Goodson
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 677-680, Washington, DC, December 3-5, 2001 []
  41. Analytical Thermal Model for Multilevel VLSI Interconnects Incorporating Via Effect
    Ting-Yen Chiang, Kaustav Banerjee and Krishna C. Saraswat
    IEEE Electron Device Letters, Vol. 23, No. 1, pp. 31-33, Jan. 2002 []
  42. Modeling and Analysis of Via Hot Spots and Implications for ULSI Interconnect Reliability
    S. Im, K. Banerjee and K. E. Goodson
    40th IEEE Annual International Reliability Physics Symposium (IRPS), pp. 336-345, Dallas, TX, April 8-11, 2002 []
  43. Via Design and Scaling Strategy for Nanometer Scale Interconnect Technologies
    S. Im, K. Banerjee and K. E. Goodson
    Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 587-590, San Francisco, December 8-11, 2002 []
  44. Modeling of Temperature Dependent Contact Resistance for Analysis of ESD Reliability
    K-H. Oh, J-H. Chun, K. Banerjee, C. Duvvury, and R. W. Dutton
    41st IEEE Annual International Reliability Physics Symposium (IRPS), pp. 249-255, Dallas, TX, March 30-April 4, 2003 []
  45. Thermal Issues in Designing Nanometer Scale Interconnects
    K. Banerjee
    20th International VLSI Multilevel Interconnection Conference (VMIC), Marina Del Rey, CA, September 22-25, 2003
    INVITED
  46. A Self-Consistent Junction Temperature Estimation Methodology for Nanometer Scale ICs with Implications for Performance and Thermal Management
    K. Banerjee, S-C. Lin, A. Keshavarzi, S. Narendra and V. De
    IEEE International Electron Devices Meeting (IEDM), pp. 887-890, Washington DC, December 7-10, 2003 []
  47. Impact of Off-state Leakage Current on Electromigration Design Rules for Nanometer Scale CMOS Technologies
    S-C. Lin, A. Basu, A. Keshavarzi, V. De and K. Banerjee
    IEEE Annual International Reliability Physics Symposium (IRPS), pp. 74-78, Phoenix, AZ, April 25-29, 2004 []
  48. Simultaneous Optimization of Supply and Threshold Voltages for Low-Power and High-Performance Circuits in the Leakage Dominant Era
    A. Basu, S-C. Lin, V. Wason, A. Mehrotra and K. Banerjee
    ACM Design Automation Conference (DAC), pp. 884-887, San Diego, CA, June 7-10, 2004 []
  49. Leakage and Variation Aware Thermal Management of Nanometer Scale ICs
    K. Banerjee, S-C. Lin, and V. Wason
    Proceedings of the IMAPS-Advanced Technology Workshop on Thermal Management, Oct. 25-27, Palo Alto, CA, 2004 []
  50. Modeling and Analysis of Non-Uniform Substrate Temperature Effects on Global ULSI Interconnects
    Amir H. Ajami, Kaustav Banerjee and Massoud Pedram
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 6, pp. 849-861, 2005 []
  51. Supply and Power Optimization in Leakage Dominant Technologies
    Man Lung Mui, Kaustav Banerjee and Amit Mehrotra
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 9, pp. 1362-1371, 2005 []
  52. Thermal Modeling of Bonded SOI/3D ICs
    R. V. Joshi, K. Banerjee, T. Smy, K. Guarini, C. T. Chuang, A. Devgan and N. Zamadmar
    Advanced Metallization Conference (AMC), pp. 25-31, Colorado Springs, CO. Sept. 26-29, 2005
  53. A Thermally Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs
    S-C. Lin, N. Srivastava and K. Banerjee
    IEEE International Conference on Computer Design (ICCD), pp. 411-416, San Jose, October 2-5, 2005 []
  54. Thermal Scaling Analysis of Multilevel Cu/Low-k Interconnect Structures in Deep Nanometer Scale Technologies
    S. Im, N. Srivastava, K. Banerjee and K. E. Goodson
    Proceedings of the 22nd International VLSI Multilevel Interconnect Conference (VMIC), pp. 525-530, Fremont, CA, October 3-6, 2005 []
    OUTSTANDING STUDENT PAPER AWARD
  55. Scaling Analysis of Multilevel Interconnect Temperatures in High Performance ICs
    Sungjun Im, Navin Srivastava, Kaustav Banerjee and Kenneth E. Goodson
    IEEE Transactions on Electron Devices, Vol. 52, No. 12, pp. 2710-2719, 2005 []
  56. Carbon Nanotube Interconnects: Implications for Performance, Power Dissipation and Thermal Management
    N. Srivastava, R. V. Joshi and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 257-260, Washington DC, Dec. 5-7, 2005 []
  57. Analysis and Implications of IC Cooling for Deep Nanometer Scale CMOS Technologies
    S-C. Lin, R. Mahajan, V. De and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 1041-1044, Washington DC, Dec. 5-7, 2005 []
    HIGHLIGHTED PAPER OF IEDM 2005
  58. Electrothermal Engineering in the Nanometer Era: From Devices and Interconnects to Circuits and Systems
    K. Banerjee, S-C. Lin, and N. Srivastava
    Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 223-230, Yokohama, Japan, Jan. 24-27, 2006 []
  59. A Thermally-Aware Performance Analysis of Vertically Integrated (3-D) Processor-Memory Hierarchy
    G. Loi, B. Agarwal, N. Srivastava, S-C. Lin, T. Sherwood and K. Banerjee
    ACM Design Automation Conference (DAC), pp. 991-996, San Francisco, CA, July 24-28, 2006 []
  60. Thermal Dissipation in Multilayer Devices
    R. V. Joshi, K. Banerjee, T. Smy, K. Guarini, C.T. Chuang and N. Zamadmar
    23rd Advanced Metallization Conference, San Diego, CA, Oct. 16-19, 2006
  61. An Electrothermally-Aware Full-Chip Substrate Temperature Gradient Evaluation Methodology for Leakage Dominant Technologies with Implications for Power Estimation and Hot-Spot Management
    S-C. Lin and K. Banerjee
    IEEE International Conference on Computer-Aided Design (ICCAD), pp. 568-574, San Jose, CA, Nov. 5-9, 2006 []
  62. Power and Thermal Challenges for 65 nm and Below
    K. Banerjee, P. Coteus and V. De
    IEEE International Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 5-9, 2006
    INVITED TUTORIAL
  63. Electrothermal Engineering in the Nanometer Era
    K. Banerjee
    17th ACM Great Lakes Symposium on VLSI (GLSVLSI), Stresa-Lago Maggiore, Italy, March 11-13, 2007
    INVITED TUTORIAL
  64. A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part I: Electrothermal Couplings and Full-Chip Package Thermal Model
    Sheng-Chih Lin, Greg Chrysler, Ravi Mahajan, Vivek De and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 54, No. 12, pp. 3342-3350, 2007 []
  65. A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part II: Implementation and Implications for Power Estimation and Thermal Management
    Sheng-Chih Lin, Greg Chrysler, Ravi Mahajan, Vivek De and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Vol. 54, No. 12, pp. 3351-3360, 2007 []
  66. Modeling and Analysis of Self-Heating in FinFET Devices for Improved Circuit and EOS/ESD Performance
    S. Kolluri, K. Endo, E. Suzuki and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 177-180, Washington DC, Dec. 10-12, 2007
  67. Carbon Nanotube Vias: A Reality Check
    H. Li, N. Srivastava, J-F. Mao, W-Y. Yin and K. Banerjee
    IEEE International Electron Devices Meeting (IEDM), pp. 207-210, Washington DC, Dec. 10-12, 2007 []
  68. Power and Thermal Management in the Nanometer Era
    K. Banerjee
    IEEE CPMT EDAPS, Taipei, Taiwan, December 15-17, 2007
  69. Thermal Challenges of 3-D ICs
    Sheng-Chih Lin and Kaustav Banerjee
    in Wafer Level 3-D ICs Process Technology, Editors: Chuan Seng Tan, Ronald J. Gutmann, L. Rafael Reif, Springer,ISBN: 978-0-387-76532-7, 2008
  70. Cool Chips: Opportunities and Implications for Power and Thermal Management
    Sheng-Chih Lin and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Special Issue on Device Technologies and Circuit Techniques for Power Management, Vol. 55, No. 1, pp. 245-255, 2008 []
    HIGHLIGHTED ON THE JOURNAL COVER
  71. A Design-Specific and Thermally-Aware Methodology for Trading-off Power and Performance in Leakage-Dominant CMOS Technologies
    Sheng-Chih Lin and Kaustav Banerjee
    IEEE Transactions on Very Large Scale Integration Systems, Vol. 16, No. 11, pp. 1488-1498, Nov. 2008 []
  72. Fast 3-D Thermal Analysis of Complex Interconnect Structures Using Electrical Modeling and Simulation Methodologies
    C. Xu, L. Jiang, S. K. Kolluri, B. J. Rubin, A. Deutsch, H. Smith, K. Banerjee
    International Conf. on Computer-Aided Design (ICCAD), San Jose, Nov. 2-5, pp. 658-665, 2009
  73. A Thermal Simulation Process Based on Electrical. Modeling for Complex Interconnect, Packaging and 3DI Structures
    Lijun Jiang, Chuan Xu, Barry J. Rubin, Alan J. Weger, Alina Deutsch, Howard Smith, Alain Caron, and Kaustav Banerjee
    IEEE Trans. Advanced Packaging, Vol. 33, No. 4, pp. 777-786, Nov. 2010. []
  74. Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability
    Chuan Xu, Seshadri K. Kolluri, Kazuhiko Endo and Kaustav Banerjee
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 7, pp. 1045-1058, 2013. []
  75. 2D Semiconductor FETs- Projections and Design for Sub-10 nm VLSI
    Wei Cao, Jiahao Kang, Deblina Sarkar, Wei Liu and Kaustav Banerjee
    IEEE Transactions on Electron Devices, Special Issue to commemorate the 60th anniversary of the IEDM, Vol. 62, No. 11, pp. 3459-3469, 2015.