Publications

2017

  1. Designing Artificial 2D Crystals with Site and Size Controlled Quantum Dots
    Xuejun Xie, Jiahao Kang, Wei Cao, Jae Hwan Chu, Yongji Gong, Pulickel M. Ajayan, and Kaustav Banerjee
  2. Boosting Hydrogen Evolution Performance of MoS2 by Band Structure Engineering
    Jing Li*, Jiahao Kang*, Qian Cai, Wentin Hong, Chuanyong Jian, Wei Liu, and Kaustav Banerjee (* Equal contributors)
  3. 2D/3D Tunnel-FET: Toward Green Transistors and Sensors
    (INVITED) Wei Cao, Jiahao Kang, and Kaustav Banerjee
  4. Characterization of Self-Heating and Current-Carrying Capacity of Intercalation Doped Graphene-Nanoribbon Interconnects
    Junkai Jiang, Jiahao Kang and Kaustav Banerjee
  5. Intercalation Doped Multilayer-Graphene-Nanoribbons for Next-Generation Interconnects
    Junkai Jiang, Jiahao Kang, Wei Cao, Xuejun Xie, Haojun Zhang, Jae Hwan Chu, Wei Liu, and Kaustav Banerjee
  6. Understanding the Device Physics in Polymer-Based Ionic-Organic Ratchets
    Y. Hu, V. Brus, W. Cao, K. Liao, H. Phan, M. Wang, K. Banerjee, G. C. Bazan, and T-Q. Nguyen

2016

  1. Effect of Band-Tails on the Subthreshold Performance of 2D Tunnel-FETs
    Haojun Zhang, Wei Cao, Jiahao Kang, and Kaustav Banerjee
  2. Prospects of Ultra-thin Nanowire Gated 2D-FETs for Next-Generation CMOS Technology
    Wei Cao, Wei Liu, and Kaustav Banerjee
  3. An Ultra-Short Channel Monolayer MoS2 FET Defined By the Curvature of a Thin Nanowire
    Wei Cao, Wei Liu, Jiahao Kang, and Kaustav Banerjee
  4. Two-Dimensional Van der Waals Materials
    Pulickel Ajayan, Philip Kim, and Kaustav Banerjee
  5. Characterization of FeCl3 Intercalation Doped CVD Few-Layer Graphene
    Wei Liu, Jiahao Kang and Kaustav Banerjee
  6. Undoped and Catalyst-Free Germanium Nanowires for High-Performance p-type Enhancement-Mode Field-Effect Transistors
    M. Simanullang, G. B. M. Wisna, K. Usami, W. Cao, Y. Kawano, K. Banerjee, S. Oda
  7. Surface Functionalization of Two-dimensional Metal Chalcogenides by Lewis Acid-Base Chemistry
    S. Lei, X. Wang, B. Li, J. Kang, Y. He, A. George, L. Ge, Y. Gong, P. Dong, Z. Jin, G. Brunetto, W. Chen, Z. Lin, R. Baines, D. S. Galvão, J. Lou, E. Barrera, K. Banerjee, R. Vajtai and P. Ajayan

2015

  1. Designing Band-to-Band Tunneling Field-Effect Transistors with 2D Semiconductors for Next-Generation Low-Power VLSI
    Wei Cao, Junkai Jiang, Jiahao Kang, Deblina Sarkar, Wei Liu, and Kaustav Banerjee
  2. Electrical Contacts to Two-dimensional Semiconductors
    Adrien Allain, Jiahao Kang, Kaustav Banerjee and Andras Kis
  3. Engineered 2D Nanomaterials–Protein Interfaces for Efficient Sensors
    K. K. Tadi, T. N Narayanan, S. Arepalli, K. Banerjee, S. Viswanathan, D. Liepmann, P. M Ajayan, V. Renugopalakrishnan
  4. ATLAS-TFET: Toward Green Transistors and Sensors
    (INVITED) K. Banerjee
    International Workshop on Dielectric Thin Films For Future Electron Devices (IWDTF), Miraikan, Tokyo, Japan, November 2-4, p. 1-4, 2015.
  5. 2D Semiconductor FETs- Projections and Design for Sub-10 nm VLSI
    Wei Cao, Jiahao Kang, Deblina Sarkar, Wei Liu and Kaustav Banerjee
  6. A Subthermionic Tunnel Field-Effect Transistor with an Atomically Thin Channel
    Deblina Sarkar, Xuejun Xie, Wei Liu, Wei Cao, Jiahao Kang, Yongji Gong, Stephan Kraemer, Pulickel M. Ajayan and Kaustav Banerjee
  7. 2D Crystals for Smart Life
    (INVITED SHORT COURSE) K. Banerjee
    47th International Conference on Solid State Devices and Materials (SSDM), Sapporo, Japan, Sept. 27-30, 2015.
  8. 2D Crystals and their Heterostructures for Green Electronics
    (INVITED) Kaustav Banerjee
    Proceedings of the 11th Topical Workshop on Heterostructure Microelectronics, Takayama, Japan, Aug 24-26, p. 10-1, 2015.
  9. Impact of Contact on the Operation and Performance of Back-Gated Monolayer MoS2 Field-Effect-Transistors
    Wei Liu, Deblina Sarkar, Jiahao Kang, Wei Cao, and Kaustav Banerjee
  10. Functionalization of Transition Metal Dichalcogenides with Metallic Nanoparticles: Implications for Doping and Gas-Sensing
    Deblina Sarkar, Xuejun Xie, Jiahao Kang, Haojun Zhang, Wei Liu, Jose Navarrete, Martin Moskovits, and Kaustav Banerjee

2014

  1. Performance Evaluation and Design Considerations of 2D Semiconductor based FETs for Sub-10 nm VLSI
    Wei Cao, Jiahao Kang, Deblina Sarkar, Wei Liu, and Kaustav Banerjee
  2. Graphene Inductors for High-Frequency Applications – Design, Fabrication, Characterization, and Study of Skin Effect
    Xiang Li*, Jiahao Kang*, Xuejun Xie, Wei Liu, Deblina Sarkar, Junfa Mao and Kaustav Banerjee (*equal contributors)
  3. Computational Study of Interfaces between 2D MoS2 and Surroundings
    Jiahao Kang, Wei Liu and Kaustav Banerjee
    45th IEEE Semiconductor Interface Specialists Conference (SISC), San Diego, CA, December 10-13, 2014.
  4. A Compact Current–Voltage Model for 2D Semiconductor Based Field-Effect Transistors Considering Interface Traps, Mobility Degradation, and Inefficient Doping Effect
    Wei Cao, Jiahao Kang, Wei Liu and Kaustav Banerjee
  5. 2D Crystal Semiconductors: Intimate Contacts
    Debdeep Jena, Kaustav Banerjee and Grace Huili Xing
    Nature Materials (News & Views), Vol. 13, pp. 1076-1078, Dec. 2014.
  6. Can 2D-Nanocrystals Extend the Lifetime of Floating-Gate Transistor Based Nonvolatile Memory?
    Wei Cao, Jiahao Kang, Simone Bertolazzi, Andras Kis and Kaustav Banerjee
  7. Computational Study of Metal Contacts to Monolayer Transition-Metal Dichalcogenide Semiconductors
    Jiahao Kang, Wei Liu, Deblina Sarkar, Debdeep Jena and Kaustav Banerjee
  8. Low-Frequency Noise in Bilayer MoS2 Transistor
    Xuejun Xie, Deblina Sarkar, Wei Liu, Jiahao Kang, Ognian Marinov, M. Jamal Deen and Kaustav Banerjee
  9. Subthreshold-Swing Physics of Tunnel Field-Effect Transistors
    Wei Cao, Deblina Sarkar, Yasin Khatami, Jiahao Kang, and Kaustav Banerjee
  10. Graphene and beyond-graphene 2D crystals for next-generation green electronics
    (INVITED) Jiahao Kang, Wei Cao, Xuejun Xie, Deblina Sarkar, Wei Liu and Kaustav Banerjee
  11. On the Electrostatic-Discharge Robustness of Graphene
    Hong Li, Christian C. Russ, Wei Liu, David Johnsson, Harald Gossner and Kaustav Banerjee
  12. Correction to MoS2 Field-Effect Transistor for Next-Generation Label-Free Biosensors
    Deblina Sarkar, Wei Liu, Xuejun Xie, Aaron Anselmo, Samir Mitragotri and Kaustav Banerjee
  13. MoS2 Field-Effect Transistor for Next-Generation Label-Free Biosensors
    Deblina Sarkar, Wei Liu, Xuejun Xie, Aaron Anselmo, Samir Mitragotri and Kaustav Banerjee
  14. Carbon Integrated Electronics
    Hong Li, Yasin Khatami, Deblina Sarkar, Jiahao Kang, Chuan Xu, Wei Liu, and Kaustav Banerjee
    in Intelligent Integrated Systems: Technologies, Devices and Architectures. Ed: S. Deleonibus, Pan Stanford Series on Intelligent Nanosystems, pp. 217-274, April 9, 2014.
  15. High-Performance MoS2 Transistors with Low-Resistance Molybdenum Contacts
    Jiahao Kang, Wei Liu and Kaustav Banerjee
  16. Controllable and Rapid Synthesis of High-Quality and Large-Area Bernal Stacked Bilayer Graphene using Chemical Vapor Deposition
    Wei Liu, Stephan Krämer, Deblina Sarkar, Hong Li, Pulickel M. Ajayan, and Kaustav Banerjee
  17. On the Electrostatics of Bernal-Stacked Few-Layer Graphene on Surface Passivated Semiconductors
    Yasin Khatami, Hong Li, Wei Liu and Kaustav Banerjee

2013

  1. High-Performance Few-Layer-MoS2 Field-Effect-Transistor with Record Low Contact-Resistance
    W. Liu, J. Kang, W. Cao, D. Sarkar, Y. Khatami, D. Jena and K. Banerjee
  2. Novel Logic Devices based on 2D Crystal Semiconductors: Opportunities and Challenges
    (INVITED) P. Zhao, W-S. Hwang, E-S. Kim, R. Feenstra, G. Gu, J. Kang, K. Banerjee, A. Seabaugh, H. Xing and D. Jena
  3. High-Performance Field-Effect-Transistors on Monolayer-WSe2
    (INVITED) W. Liu, W. Cao, J. Kang, and K. Banerjee
  4. 2-Dimensional Tunnel Devices and Circuits on Graphene: Opportunities and Challenges
    Jiahao Kang, Wei Cao, Deblina Sarkar, Yasin Khatami, Wei Liu and Kaustav Banerjee
  5. Prospects of nanoCarbons and Emerging 2D-Crystals for Next-Generation Green Electronics
    (INVITED) K. Banerjee
    Advanced Metallization Conference 2013: 23rd Asian Session, The University of Tokyo, Tokyo, Japan, Oct. 7-10, 2013, pp. 1-2.
  6. Prospects of Graphene Electrodes in Photovoltaics
    (INVITED) Y. Khatami, W. Liu, J. Kang and K. Banerjee
  7. 2D Electronics: Graphene and Beyond
    (KEYNOTE) W. Cao, J. Kang, W. Liu, Y. Khatami, D. Sarkar and K. Banerjee
    43rd European Solid-State Device Research Conference (ESSDERC), Bucharest, Romania, Sept. 16-20, 2013, pp. 1-8. Slides: []
  8. Low-Resistivity Long-Length Horizontal Carbon Nanotube Bundles for Interconnect Applications – Part I: Process Development
    Hong Li, Wei Liu, Alan M. Cassell, Franz Kreupl and Kaustav Banerjee
  9. Low-Resistivity Long-Length Horizontal Carbon Nanotube Bundles for Interconnect Applications – Part II: Characterization
    Hong Li, Wei Liu, Alan M. Cassell, Franz Kreupl and Kaustav Banerjee
  10. Proposal for All-Graphene Monolithic Logic Circuits
    Jiahao Kang, Deblina Sarkar, Yasin Khatami and Kaustav Banerjee
  11. Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability
    Chuan Xu, Seshadri K. Kolluri, Kazuhiko Endo and Kaustav Banerjee
  12. Graphene and Beyond-Graphene 2D-Crystals for Green Electronics
    (INVITED) K. Banerjee, W. Liu, J. Kang, Y. Khatami and D. Sarkar
    18th Silicon Nanoelectronics Workshop, Kyoto, Japan, June 9-10, 2013, pp. 1-2.
  13. Impact-Ionization Field-Effect-Transistor Based Biosensors for Ultra-Sensitive Detection of Biomolecules
    Deblina Sarkar, Harald Gossner, Walter Hansch and Kaustav Banerjee
  14. VLSI Technology and Circuits
    K. Banerjee and S. Ikeda
  15. Role of Metal Contacts in Designing High-Performance Monolayer n-Type WSe2 Field-Effect-Transistors
    Wei Liu, Jiahao Kang, Deblina Sarkar, Yasin Khatami, Debdeep Jena and Kaustav Banerjee
  16. Graphene nanoribbon based negative resistance device for ultra-low voltage digital logic applications
    Yasin Khatami, Jiahao Kang, and Kaustav Banerjee
  17. Tunnel-Field-Effect-Transistor Based Gas-Sensor: Introducing Gas Detection with a Quantum-Mechanical Transducer
    Deblina Sarkar, Harald Gossner, Walter Hansch and Kaustav Banerjee
  18. Physical Modeling of the Capacitance and Capacitive Coupling-Noise of Through-Oxide Vias in FDSOI Based Ultra-High Density 3-D ICs
    Chuan Xu and Kaustav Banerjee

2012

  1. A Computational Study of Metal-Contacts to Beyond-Graphene 2D Semiconductor Materials
    Jiahao Kang, Deblina Sarkar, Wei Liu, Debdeep Jena and Kaustav Banerjee
  2. Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs with Multiple Substrates
    Chuan Xu, Navin Srivastava, Roberto Suaya and Kaustav Banerjee
  3. Some Clarifications on “Compact Modeling and Analysis of Through-Si-Via Induced Electrical Noise Coupling in Three-Dimensional ICs
    Chuan Xu, Roberto Suaya and Kaustav Banerjee
  4. ESD Characterization of Atomically-Thin Graphene
    H. Li, C. Russ, W. Liu, D. Johnsson, H. Gossner and K. Banerjee
  5. Metal to Multi-Layer Graphene Contact--Part I: Contact Resistance Modeling
    Yasin Khatami, Hong Li, Chuan Xu, and Kaustav Banerjee
  6. Metal to Multi-Layer Graphene Contact--Part II: Analysis of Contact Resistance
    Yasin Khatami, Hong Li, Chuan Xu, and Kaustav Banerjee
  7. Top Illuminated Inverted Organic UV Photosensors With Single Layer Graphene Electrodes
    Martin Burkhardt, Wei Liu, Christopher G. Shuttle, Kaustav Banerjee, and Michael L. Chabinyc
  8. NEMS based Ultra Energy-Efficient Digital ICs: Materials, Device Architectures, Logic Implementation, and Manufacturability
    H. F. Dadgour and K. Banerjee
    Chapter 10 in Microelectronics to Nanoelectronics: Materials, Devices & Manufacturability. Ed: Anupama B. Kaul, CRC Press, ISBN 9781466509542, July 2012.
  9. Fundamental Limitations of Conventional-FET Biosensors: Quantum-Mechanical-Tunneling to the Rescue
    D. Sarkar and K. Banerjee
  10. Fast Extraction of High-Frequency Parallel Admittance of Through-Silicon-Vias and their Capacitive Coupling-Noise to Active Regions
    C. Xu, R. Suaya and K. Banerjee
  11. Proposal for Tunnel-Field-Effect-Transistor as Ultra-Sensitive and Label-Free Biosensors
    Deblina Sarkar and Kaustav Banerjee

2011

  1. Graphene Based Green Electronics
    K. Banerjee
    International Workshop on Physics of Semiconductors (IWPSD), IIT-Kanpur, India, Dec 18-22, 2011.
    INVITED TALK
  2. Graphene Based Green Electronics
    K. Banerjee
    IEEE Electrical Design of Advanced Packaging & Systems (EDAPS) Symposium, Hangzhou, China, Dec 12-14, 2011.
    KEYNOTE
  3. Some Results Pertaining Electromagnetic Characterization and Model Building for Passive Systems Including TSVs, for 3-D IC’s Applications
    R. Suaya , C. Xu , V Kourkoulos , K Banerjee, Z. Mahmood and L. Daniel
  4. Future of Carbon Nanomaterials as Next-Generation Interconnects and Passives Devices
    Hong Li, Chuan Xu, Deblina Sarkar, Yasin Khatami, Wei Liu and Kaustav Banerjee
    IEEE Electrical Design of Advanced Packaging & Systems (EDAPS) Symposium, Hangzhou, China, Dec 12-14, 2011
  5. Compact Capacitance and Capacitive Coupling-Noise Modeling of Through-Oxide Vias in FDSOI Based Ultra-High Density 3-D ICs
    C. Xu and K. Banerjee
  6. Compact Modeling and Analysis of Through-Si-Via Induced Electrical Noise Coupling in 3-D ICs
    Chuan Xu, Roberto Suaya and Kaustav Banerjee
  7. CMOS Compatible Vertical Silicon Nanowire Gate-All-Around p-type Tunneling FETs with ≤50 mV/decade Subthreshold Swing
    Ramanathan Gandhi, Zhixian Chen, Navab Singh, Kaustav Banerjee and Sungjoo Lee
  8. Vertically Stacked and Independently Controlled Twin-Gate MOSFETs on a Single Si-Nanowire
    Xiang Li, Zhixian Chen, Nansheng Shen, Deblina Sarkar, Navab Singh, Kaustav Banerjee, Guo-Qiang Lo and Dim-Lee Kwong
  9. Synthesis of High-Quality Monolayer and Bilayer Graphene on Copper using Chemical Vapor Deposition
    Wei Liu, Hong Li, Chuan Xu, Yasin Khatami and Kaustav Banerjee
  10. A Physical Model for Work-Function Variation in Ultra-Short Channel Metal-Gate MOSFETs
    Seid Hadi Rasouli, Chuan Xu, Navab Singh and Kaustav Banerjee
  11. A Fully Analytical Model for the Series Impedance of Through-Silicon Vias with Consideration of Substrate Effects and Coupling with Horizontal Interconnects
    Chuan Xu, Vassilis Kourkoulos, Roberto Suaya and Kaustav Banerjee
  12. Metallic-Nanoparticle Assisted Enhanced Band-to-Band Tunneling Current
    Deblina Sarkar and Kaustav Banerjee
  13. Carbon Nanotube Vias: Does Ballistic Electron-Phonon Transport Imply Improved Performance and Reliability?
    Hong Li, Navin Srivastava, Jun-Fa Mao, Wen-Yan Yin and Kaustav Banerjee
  14. Grain-Orientation Induced Quantum Confinement Variation in FinFETs and Multi-Gate Ultra-Thin Body CMOS Devices and Implications for Digital Design
    Seid Hadi Rasouli, Kazuhiko Endo, Jone F. Chen, Navab Singh and Kaustav Banerjee
  15. Demonstration of Vertical Silicon Nanowire Tunnel Field Effect Transistor with Low Subthreshold Slope < 50mV/decade
    R. Gandhi, Z. X. Chen, N. Singh, K. Banerjee, and S. J. Lee
    International Conference on Materials for Advanced Technologies (ICMAT), Singapore, June 26-July 1, 2011.
  16. Impact of Scaling on the Performance and Reliability Degradation of Metal-Contacts in NEMS Devices
    H. F. Dadgour, M. M. Hussain, A. Cassell, N. Singh and K. Banerjee
  17. Vertical Si-Nanowire n-Type Tunneling FETs With Low Subthreshold Swing (≤ 50 mV/decade) at Room Temperature
    Ramanathan Gandhi, Zhixian Chen, Navab Singh, Kaustav Banerjee, and Sungjoo Lee
  18. Carbon Based Green Electronics
    K. Banerjee
    ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU 2011), Santa Barbara, CA, March 31-April 1, 2011.
    KEYNOTE
  19. High-Frequency Behavior of Graphene-Based Interconnects—Part II: Impedance Analysis and Implications for Inductor Design
    Deblina Sarkar, Chuan Xu, Hong Li, and Kaustav Banerjee
  20. High-Frequency Behavior of Graphene-Based Interconnects—Part I: Impedance Modeling
    Deblina Sarkar, Chuan Xu, Hong Li, and Kaustav Banerjee
  21. Factors Influencing the Synthesis of Monolayer and Bilayer Graphene on Copper using Chemical Vapor Deposition
    Wei Liu, Hong Li, Chuan Xu and Kaustav Banerjee
    38th Conference on the Physics and Chemistry of Surfaces and Interfaces (PCSI-38), San Diego, CA, January 16-20, 2011.

2010

  1. Electron-hole Duality During Band-to-Band Tunneling Process in Graphene-Nanoribbon Tunnel-Field-Effect Transistors
    Deblina Sarkar, Michael Krall, and Kaustav Banerjee
  2. A Quantitative Inquisition into ESD Sensitivity to Strain in Nanoscale CMOS Protection Devices
    D. Sarkar, S. Thijs, D. Linten, C. Russ, H. Gossner and K. Banerjee
  3. Compact Modeling and Analysis of Coupling Noise Induced by Through-Si-Vias in 3-D ICs
    C. Xu, R. Suaya and K. Banerjee
  4. Compact AC Modeling and Performance Analysis of Through-Silicon Vias (TSVs) in 3-D ICs
    Chuan Xu, Hong Li, Roberto Suaya and Kaustav Banerjee
  5. Carbon-Based Green Electronics
    Kaustav Banerjee
    Materials Research Society (MRS) Fall Symposium, Boston, MA, Nov. 29-Dec. 3, 2010. (INVITED)
  6. Work-function variation induced fluctuation in bias-temperature-instability characteristics of emerging metal-gate devices and implications for digital design
    S. H. Rasouli, K. Endo, and K. Banerjee
  7. Design Optimization of FinFET Domino Logic Considering the Width Quantization Property
    Seid Hadi Rasouli, Hamed F. Dadgour, Kazuhiko Endo, Hanpei Koike, and Kaustav Banerjee
  8. A Thermal Simulation Process Based on Electrical. Modeling for Complex Interconnect, Packaging and 3DI Structures
    Lijun Jiang, Chuan Xu, Barry J. Rubin, Alan J. Weger, Alina Deutsch, Howard Smith, Alain Caron, and Kaustav Banerjee
  9. A Novel Enhanced Electric-Field Impact-Ionization MOS Transistor
    Deblina Sarkar, Navab Singh and Kaustav Banerjee
  10. A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-in Dynamic Gates
    Hamed Dadgour and Kaustav Banerjee
  11. Grain-Orientation Induced Work-Function Variation in Nanoscale Metal-Gate Transistors––Part II: Implications for Process, Device, and Circuit Design
    Hamed F. Dadgour, Kazuhiko Endo, Vivek De, and Kaustav Banerjee
  12. Grain-Orientation Induced Work-Function Variation in Nanoscale Metal-Gate Transistors––Part I: Modeling, Analysis, and Experimental Validation
    Hamed F. Dadgour, Kazuhiko Endo, Vivek De, and Kaustav Banerjee
  13. A New Paradigm in the Design of Energy-Efficient Digital Circuits Using Laterally-Actuated Double-Gate NEMS
    H.F. Dadgour, M.M. Hussain and K. Banerjee
  14. Prospects of Carbon Nanomaterials for Next-Generation Green Electronics
    K. Banerjee, H. Li, C. Xu, Y. Khatami, H.F. Dadgour, D. Sarkar and W. Liu
  15. Accurate Calculations of the High-frequency Impedance Matrix for VLSI Interconnects and Inductors above a Multi-layer Substrate: A VARPRO success story
    N. Srivastava, R. Suaya, V. Pereyra and K. Banerjee
    in Exponential Data Fitting and its Applications, Editors: V. Pereyra and G. Scherer. Bentham Science Publishers, ISBN: 978-1-60805-048-2, 2010.
  16. Carbon Nanomaterials: The Ideal Interconnect Technology for Next-Generation ICs
    Hong Li, Chuan Xu, and Kaustav Banerjee
    INVITED
  17. Effect of Grain Orientation on NBTI Variation and Recovery in Emerging Metal-Gate Devices
    Seid Hadi Rasouli and Kaustav Banerjee
  18. Compact AC Modeling and Performance Analysis of Through-Silicon Vias (TSVs) in 3-D ICs
    C. Xu, H. Li, R. Suaya and K. Banerjee
  19. Graphene Based Heterostructure Tunnel-FETs for Low-Voltage/High-Performance ICs
    Y. Khatami, M. Krall, H. Li., C. Xu., K. Banerjee
  20. CAD for Nanoelectronics: Earlier the Better
    K. Banerjee
    IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH’08), June 17-18, 2010, Anaheim, CA PANEL: CAD for Nanoelectronic Circuits and Architectures – Are we there yet?
  21. Design and Analysis of Compact Ultra Energy-Efficient Logic Gates Using Laterally-Actuated Double-Electrode NEMS
    H. F. Dadgour, M. M. Hussain, C. Smith and K. Banerjee
  22. An Efficient 3D Green’s Function Approach for Fast Impedance Extraction of Interconnects and Spiral Inductors in CMOS RF/Millimeter-wavelength Circuits
    N. Srivastava, R. Suaya and K. Banerjee
  23. AC Conductance Modeling and Analysis of Graphene Nanoribbon Interconnects
    D. Sarkar, C. Xu, H. Li, and K. Banerjee
  24. A Built-in Aging Detection and Compensation Technique for Improving Reliability of Nanoscale CMOS Designs
    H. Dadgour and K. Banerjee
  25. Corrections to “Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate”
    Navin Srivastava, Chuan. Xu, Roberto Suaya, and Kaustav Banerjee
  26. Carbon based Nanomaterials as Interconnects and Passives for Next-Generation VLSI and 3-D ICs
    K. Banerjee
    IEEE WMED, Boise, Idaho, April 16, 2010
    INVITED TUTORIAL
  27. Carbon Based Active and Passive Devices for Next-Generation ICs
    K. Banerjee, W. Liu, H. Li, Y.Khatami, and C. Xu
    Ultimate Limit of Integration in Silicon (ULIS), Glasgow, Scotland, March 17-19, 2010.
    INVITED--PLENARY
  28. Efficient 3D High-frequency Impedance Extraction for General Interconnects and Inductors Above a Layered Substrate
    N. Srivastava, R. Suaya and K. Banerjee
  29. Aging-Resilient Design of Pipelined Architectures using Novel Detection and Correction Circuits
    H. Dadgour and K. Banerjee

2009

  1. Single wall carbon nanotube-Aptamer Based Biosensors
    S. H. Varghese, Y. Nakajima, Y. Yoshida, T. Maekawa, T. Hanajiri, K. Banerjee, D. S. Kumar
    7 th International Symposium on Bioscience and Nanotechnology, Tokyo, Japan, December 20-21, 2009.
  2. Carbon Nanomaterial based Interconnects and Passives for Next-Generation ICs
    K. Banerjee, H. Li and C. Xu
    XVth International Workshop on Physics of Semiconductor Devices (IWPSD), New Delhi India, Dec. 15-19, 2009
  3. Compact AC Modeling and Analysis of Cu, W, and CNT based Through-Silicon Vias (TSVs) in 3-D ICs
    C. Xu, H. Li, R. Suaya, K. Banerjee
  4. Impact of Strain Engineering and Channel Orientation on the ESD Performance of Nanometer Scale CMOS Devices
    J. Lu, C. Duvvury, H. Gossner and K. Banerjee
  5. Green Electronics using Graphene based Nanomaterials
    K. Banerjee
    Emerging Technologies in Solid State Devices Workshop, Baltimore, MD, December 5 - 6, 2009
  6. Experimental Investigation of ESD Performance for Strained Silicon Nano-Devices
    D. Sarkar, H. Gossner and K. Banerjee
    ESD Forum, Berlin, Dec. 1-2, 2009
  7. Fast 3-D Thermal Analysis of Complex Interconnect Structures Using Electrical Modeling and Simulation Methodologies
    C. Xu, L. Jiang, S. K. Kolluri, B. J. Rubin, A. Deutsch, H. Smith, K. Banerjee
  8. Variability Analysis of FinFET-Based Devices and Circuits Considering Electrical Confinement and Width Quantization
    S.H. Rasouli, K. Endo, and K. Banerjee
  9. Hybrid NEMS-CMOS Integrated Circuits: A Novel Strategy for Energy-Efficient Designs
    Hamed Dadgour and Kaustav Banerjee
  10. Steep Subthreshold Slope n- and p-type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits
    Yasin Khatami and Kaustav Banerjee
  11. Carbon Based Active and Passive Devices for Next-Generation ICs
    K. Banerjee, H. Dadgour, Y. Khatami, H. Li, C. Xu
    Global COE International Symposium on Silicon Nano Devices in 2030: Prospects by World’s Leading Scientists, Oct. 13-14, Tokyo, 2009
  12. Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status and Prospects
    K. Banerjee, H. Li and C. Xu
    International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, Oct. 7-9, 2009
  13. High-Frequency Analysis of Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design
    Hong Li and Kaustav Banerjee
  14. Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status and Prospects
    Hong Li, Chuan Xu, Navin Srivastava, and Kaustav Banerjee
    INVITED AND HIGHLIGHTED ON THE JOURNAL COVERPAGE
  15. Prospects of Carbon Nanomaterials in VLSI for Interconnections and Energy Storage
    K. Banerjee, H. Li and C. Xu
  16. An Analytical Treatment of High-frequency Impedance Extraction for Interconnects and Inductors in the Presence of a Multi-layer Substrate
    R. Suaya, N. Srivastava and K. Banerjee
    Progress in Electromagnetics Research Symposium (PIERS), Moscow, Russia, August 18-21, 2009
  17. Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status and Prospects
    K. Banerjee, H. Li, N. Srivastava and C. Xu
    Progress in Electromagnetics Research Symposium (PIERS), Moscow, Russia, August 18-21, 2009
  18. Modeling, Analysis and Design of Graphene Nano-Ribbon Interconnects
    Chuan Xu, Hong Li, and Kaustav Banerjee
  19. Graphene Based Nanomaterials for VLSI Interconnect and Energy-Storage Applications
    K. Banerjee
    ACM/IEEE System Level Interconnect Prediction (SLIP), San Francisco, CA, July 26, 2009
    INVITED PANEL
  20. Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multi-layer Conductive Substrate
    Navin Srivastava, Roberto Suaya and Kaustav Banerjee
  21. On the Applicability of Single-Walled Carbon Nanotubes as VLSI Interconnections
    Navin Srivastava, Hong Li, Franz Kreupl, and Kaustav Banerjee
  22. Scaling Analysis of Graphene Nanoribbon Tunnel-FETs
    Y. Khatami and K. Banerjee
  23. Carbon Nanomaterials for Next Generation Interconnects and Passives: Physics, Status and Prospects
    K. Banerjee
    International Electrostatic Discharge Workshop (IEW), Lake Tahoe, CA, May 18-21, 2009
    KEYNOTE
  24. Graphene Based Transistors: Physics, Status and Future Perspectives
    K. Banerjee, Y. Khatami, C. Kshirsagar, S. H. Rasouli
  25. Carbon Nanomaterials for Next Generation Interconnects and Passives: Physics, Status and Prospects
    K. Banerjee
    18th Materials for Advanced Metallization Conference (MAM), Grenoble, France, March 8-11
  26. CMOS vs. Nano: Comrades or Rivals?
    K. Banerjee
    INVITED PANEL
  27. High-Speed Low-Power FinFET Based Domino Logic
    S. H. Rasouli, H. Koike and K. Banerjee

2008

  1. Modeling and Analysis of Grain-Orientation Effects in Emerging Metal-Gate Devices and Implications for SRAM Reliability
    H. Dadgour, K. Endo, V. De and K. Banerjee
  2. Scaling and Variability Analysis of CNT-Based NEMS Devices and Circuits with Implications for Process Design
    H. Dadgour, A. M. Cassell and K. Banerjee
  3. High-Frequency Effects in Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design
    H. Li and K. Banerjee
  4. Graphene Nano-Ribbon (GNR) Interconnects: A Genuine Contender or a Delusive Dream?
    C. Xu, H. Li and K. Banerjee
  5. Accurate Intrinsic Gate Capacitance Model for Carbon Nanotube-Array Based FETs Considering Screening Effect
    Chaitanya Kshirsagar, Hong Li, Tom Kopley, and Kaustav Banerjee
  6. Statistical Modeling of Metal-Gate Work-Function Variability in Emerging Device Technologies and Implications for Circuit Design
    H. Dadgour, V. De and K. Banerjee
    Nominated for the BEST PAPER AWARD
  7. A Design-Specific and Thermally-Aware Methodology for Trading-off Power and Performance in Leakage-Dominant CMOS Technologies
    Sheng-Chih Lin and Kaustav Banerjee
  8. Current Status and Future Perspectives of Carbon Nanotube Interconnects
    K.Banerjee, H. Li and N. Srivastava
    IEEE EMC Symposium, Detroit, MI, August 18-22, 2008. (INVITED)
  9. Current Status and Future Perspectives of Carbon Nanotube Interconnects
    K. Banerjee, H. Li and N. Srivastava
  10. Carbon Nanotube Interconnects for Next Generation ICs
    K. Banerjee
    Summer School on Nanoelectronic Circuits and Tools, EPFL, Lausanne, Switzerland, July 14-18, 2008
    INVITED
  11. Hybrid NEMS-CMOS Circuits
    K. Banerjee
    IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH’08), June 12-13, 2008, Anaheim, CA Panel: Non-CMOS NanoElectronics – Will it ever be real?
    INVITED PANEL
  12. Analysis and Implications of Parasitic and Screening Effects on the High-Frequency/RF Performance of Tunneling-Carbon Nanotube FETs
    C. Kshirsagar, M. N. El-Zeftawi and K. Banerjee
  13. Circuit Modeling and Performance Analysis of Multi-Walled Carbon Nanotube Interconnects
    Hong Li, Wen-Yan Yin, Kaustav Banerjee, and Jun-Fa Mao
  14. High-Frequency Effects in Carbon Nanotube Interconnects
    K. Banerjee
    12th IEEE Workshop on Signal Propagation on Interconnects (SPI), Avignon, Pope's Palace, France, May 12-15, 2008
    KEYNOTE
  15. 3D Device Modeling of Damage Due to Filamentation Under an ESD Event in Nanometer Scale Drain Extended NMOS (DE-NMOS)
    A. Chatterjee, S. Pendharkar, H. Gossner, C. Duvvury and K. Banerjee
  16. High-Frequency Mutual Impedance Extraction of VLSI Interconnects in the Presence of a Multi-layer Conducting Substrate
    N. Srivastava, R. Suaya and K. Banerjee
  17. Cool Chips: Opportunities and Implications for Power and Thermal Management
    Sheng-Chih Lin and Kaustav Banerjee
    HIGHLIGHTED ON THE JOURNAL COVER
  18. Thermal Challenges of 3-D ICs
    Sheng-Chih Lin and Kaustav Banerjee
    in Wafer Level 3-D ICs Process Technology, Editors: Chuan Seng Tan, Ronald J. Gutmann, L. Rafael Reif, Springer,ISBN: 978-0-387-76532-7, 2008

2007

  1. Power and Thermal Management in the Nanometer Era
    K. Banerjee
    IEEE CPMT EDAPS, Taipei, Taiwan, December 15-17, 2007
  2. Performance Analysis of Multi-Walled Carbon Nanotube Based Interconnects
    H. Li, W-Y. Yin, J-F. Mao and K. Banerjee
  3. Modeling and Analysis of Intrinsic Gate Capacitance for Carbon Nanotube Array Based Devices Considering Variaion in Screening Effect and Diameter
    C. Kshirsagar and K. Banerjee
  4. A Fast Semi-numerical Technique for the Solution of the Poisson-Boltzmann Equation in a Cylindrical Nanowire
    A. Ramu, M. P. Anantram and K. Banerjee
  5. Carbon Nanotube Vias: A Reality Check
    H. Li, N. Srivastava, J-F. Mao, W-Y. Yin and K. Banerjee
  6. Modeling and Analysis of Self-Heating in FinFET Devices for Improved Circuit and EOS/ESD Performance
    S. Kolluri, K. Endo, E. Suzuki and K. Banerjee
  7. A Microscopic Understanding of Nanometer Scale DENMOS Failure Mechanism Under ESD Conditions
    A. Chatterjee, S. Pendharkar, Y-Y. Lin, C. Duvvury and K. Banerjee
  8. A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part II: Implementation and Implications for Power Estimation and Thermal Management
    Sheng-Chih Lin, Greg Chrysler, Ravi Mahajan, Vivek De and Kaustav Banerjee
  9. A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part I: Electrothermal Couplings and Full-Chip Package Thermal Model
    Sheng-Chih Lin, Greg Chrysler, Ravi Mahajan, Vivek De and Kaustav Banerjee
  10. A Statistical Framework for Estimation of Full-Chip Leakage-Power Distribution under Parameter Variations
    Hamed Dadgour, Sheng-Chih Lin and Kaustav Banerjee
  11. Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications
    H. F. Dadgour and K. Banerjee
  12. Nano-enhanced Architectures: Using Carbon Nanotube Interconnects in Cache Design
    B. Agrawal, N. Srivastava, F. T. Chong, K. Banerjee and T. Sherwood
    4th Workshop on Non-Silicon Computing (NSC-4) held in conjunction with the International Symposium on Computer Architecture (ISCA'07 workshop), San Diego, California, June 2007
  13. An Insight into the High Current ESD Behavior of Drain Extended NMOS (DENMOS) Devices in Nanometer Scale CMOS Technologies
    A. Chatterjee, S. Pendharkar, Y-Y. Lin , C. Duvvury and K. Banerjee
  14. Electrothermal Engineering in the Nanometer Era
    K. Banerjee
    17th ACM Great Lakes Symposium on VLSI (GLSVLSI), Stresa-Lago Maggiore, Italy, March 11-13, 2007
    INVITED TUTORIAL
  15. SoC Communication Architectures: Technology, Current Practice, Research and Trends
    K. Banerjee, L. Benini, N. Dutt, K. Lahiri and S. Pasricha
    VLSI Design Conference, Bangalore, India, Jan. 6-10, 2007
    INVITED TUTORIAL
  16. 3D-Integration for Introspection
    Shashidhar Mysore, Banit Agrawal, Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee and Timothy Sherwood

2006

  1. Can Carbon Nanotubes Extend the Lifetime of On-Chip VLSI Interconnections?
    K. Banerjee
  2. Power and Thermal Challenges for 65 nm and Below
    K. Banerjee, P. Coteus and V. De
    IEEE International Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 5-9, 2006
    INVITED TUTORIAL
  3. An Electrothermally-Aware Full-Chip Substrate Temperature Gradient Evaluation Methodology for Leakage Dominant Technologies with Implications for Power Estimation and Hot-Spot Management
    S-C. Lin and K. Banerjee
  4. What are Carbon Nanotubes?
    K. Banerjee
    ACM SIGDA Newsletter, Vol. 36, No. 21, Nov. 2006
  5. Introspective 3-D Chips
    S. C. Mysore, B. Agrawal, N. Srivastava, S-C. Lin, K. Banerjee and T. Sherwood
    IEEE MICRO Top Pick
  6. Carbon Nanotubes: An Emerging Alternative for On-Chip VLSI Interconnects
    K. Banerjee
    Future Directions in IC and Package Design Workshop, (FDIP), Scottsdale, AZ, Oct. 22, 2006
  7. Thermal Dissipation in Multilayer Devices
    R. V. Joshi, K. Banerjee, T. Smy, K. Guarini, C.T. Chuang and N. Zamadmar
    23rd Advanced Metallization Conference, San Diego, CA, Oct. 16-19, 2006
  8. Modeling and Extraction of Nanometer Scale Interconnects: Challenges and Opportunities
    R. Suaya, R. Escovar, S. Ortiz, K. Banerjee and N. Srivastava
    23rd Advanced Metallization Conference, San Diego, CA, Oct. 16-19, 2006 []
  9. Prospects for Carbon Nanotube Interconnects
    K. Banerjee
    23rd Advanced Metallization Conference (AMC), San Diego, CA, Oct. 16-19, 2006
  10. Can Carbon Nanotubes Extend the Lifetime of On-Chip Electrical Interconnections?
    K. Banerjee, S. Im and N. Srivastava
    IEEE Conference on Nano Networks (Nano-Net), Lausanne, Switzerland, Sept. 14-16, 2006
  11. Are Carbon Nanotubes the Future of VLSI Interconnections?
    K. Banerjee and N. Srivastava
  12. A Novel Variation-Aware Low-Power Keeper Architecture for Wide Fan-in Dynamic Gates
    H. F. Dadgour, R. V. Joshi and K. Banerjee
  13. A Thermally-Aware Performance Analysis of Vertically Integrated (3-D) Processor-Memory Hierarchy
    G. Loi, B. Agarwal, N. Srivastava, S-C. Lin, T. Sherwood and K. Banerjee
  14. Emerging Interconnect Technologies based on Carbon Nanotubes
    N. Srivastava and K. Banerjee
    IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 27-29, 2006
    INVITED TUTORIAL
  15. Electrothermal Engineering in the Nanometer Era: From Devices and Interconnects to Circuits and Systems
    K. Banerjee, S-C. Lin, and N. Srivastava

2005

  1. Analysis and Implications of IC Cooling for Deep Nanometer Scale CMOS Technologies
    S-C. Lin, R. Mahajan, V. De and K. Banerjee
    HIGHLIGHTED PAPER OF IEDM 2005
  2. Carbon Nanotube Interconnects: Implications for Performance, Power Dissipation and Thermal Management
    N. Srivastava, R. V. Joshi and K. Banerjee
  3. New Physical Insight and Modeling of Second Breakdown (It2) Phenomenon in Advanced ESD Protection Devices
    A. Chatterjee, C. Duvvury and K. Banerjee
  4. Scaling Analysis of Multilevel Interconnect Temperatures in High Performance ICs
    Sungjun Im, Navin Srivastava, Kaustav Banerjee and Kenneth E. Goodson
  5. Performance Analysis of Carbon Nanotube Interconnects for VLSI Applications
    N. Srivastava and K. Banerjee
  6. Thermal Scaling Analysis of Multilevel Cu/Low-k Interconnect Structures in Deep Nanometer Scale Technologies
    S. Im, N. Srivastava, K. Banerjee and K. E. Goodson
    Proceedings of the 22nd International VLSI Multilevel Interconnect Conference (VMIC), pp. 525-530, Fremont, CA, October 3-6, 2005
    OUTSTANDING STUDENT PAPER AWARD
  7. A Thermally Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs
    S-C. Lin, N. Srivastava and K. Banerjee
  8. Interconnect Modeling and Analysis in the Nanometer Era: Cu and Beyond
    K. Banerjee, S. Im and N. Srivastava
    Advanced Metallization Conference (AMC), Colorado Springs, CO. Sept. 26-29, 2005 []
  9. Thermal Modeling of Bonded SOI/3D ICs
    R. V. Joshi, K. Banerjee, T. Smy, K. Guarini, C. T. Chuang, A. Devgan and N. Zamadmar
    Advanced Metallization Conference (AMC), pp. 25-31, Colorado Springs, CO. Sept. 26-29, 2005
  10. Supply and Power Optimization in Leakage Dominant Technologies
    Man Lung Mui, Kaustav Banerjee and Amit Mehrotra
  11. A Probabilistic Framework for Power-Optimal Repeater Insertion for Global Interconnects Under Parameter Variations
    V. Wason and K. Banerjee
    Nominated for the BEST PAPER AWARD
  12. Modeling and Analysis of Non-Uniform Substrate Temperature Effects on Global ULSI Interconnects
    Amir H. Ajami, Kaustav Banerjee and Massoud Pedram
  13. Mechanisms Leading to Erratic Snapback Behavior in Bipolar Junction Transistors with Base Emitter Shorted
    Amitabh Chatterjee, Ronald D. Schrimpf, Sameer Pendharkar and Kaustav Banerjee
  14. Impact of On-Chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits
    N. Srivastava, X. Qi and K. Banerjee
  15. Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI
    Amir H. Ajami, Kaustav Banerjee and Massoud Pedram
  16. Emerging Nanoelectronics: Life With and After CMOS, Vol. 3
    Adrian M. Ionescu and Kaustav Banerjee
    Springer (Kluwer), ISBN: 1-4020-7916-8, 428 pp. (2005)
  17. Emerging Nanoelectronics: Life With and After CMOS, Vol. 2
    Adrian M. Ionescu and Kaustav Banerjee
    Springer (Kluwer), ISBN: 1-4020-7915-X, 340 pp. (2005)
  18. Emerging Nanoelectronics: Life With and After CMOS, Vol. 1,
    Adrian M. Ionescu and Kaustav Banerjee
    Springer (Kluwer), ISBN: 1-4020-7533-2, 622 pp. (2005)

2004

  1. Analytical Modelling of Single Electron Transistor (SET) for Hybrid CMOS-SET Analog IC Design
    Santanu Mahapatra, Vaibhav Vaish, Christoph Wasshuber, Kaustav Banerjee and Adrian Ionescu
  2. Leakage and Variation Aware Thermal Management of Nanometer Scale ICs
    K. Banerjee, S-C. Lin, and V. Wason
    Proceedings of the IMAPS-Advanced Technology Workshop on Thermal Management, Oct. 25-27, Palo Alto, CA, 2004 []
  3. Interconnect Challenges for Nanoscale Electronic Circuits
    Navin Srivastava and Kaustav Banerjee
    TMS Journal of Materials (JOM), Special Issue on Nanoelectronics, Vol. 56, No. 10, pp. 30-31, October 2004 []
    INVITED
  4. A Comparative Scaling Analysis of Metallic and Carbon Nanotube Interconnections for Nanometer Scale VLSI Technologies
    N. Srivastava and K. Banerjee
    Proceedings of the 21st International VLSI Multilevel Interconnect Conference (VMIC), pp. 393-398, Hawaii, Sept. 29-Oct. 2, 2004 []
  5. Nanometer Scale Interconnect Challenges
    K. Banerjee
    State-Of-The-Art Seminar, 21st International VLSI Multilevel Interconnection Conference (VMIC), Hawaii, Sept. 29-Oct. 2, 2004
  6. A Probabilistic Framework to Estimate Full-Chip Subthreshold Leakage Power Distribution Considering Within-Die and Die-to-Die P-T-V Variations
    S. Zhang, V. Wason and K. Banerjee
  7. Simultaneous Optimization of Supply and Threshold Voltages for Low-Power and High-Performance Circuits in the Leakage Dominant Era
    A. Basu, S-C. Lin, V. Wason, A. Mehrotra and K. Banerjee
  8. Modeling Techniques and Verification Methodologies for Substrate Coupling Effects in Mixed-Signal System-on-Chip Designs
    Adil Koukab, Kaustav Banerjee and Michel Declercq
  9. Impact of Off-state Leakage Current on Electromigration Design Rules for Nanometer Scale CMOS Technologies
    S-C. Lin, A. Basu, A. Keshavarzi, V. De and K. Banerjee
    IEEE Annual International Reliability Physics Symposium (IRPS), pp. 74-78, Phoenix, AZ, April 25-29, 2004
  10. Power Supply Optimization in Sub-130 nm Leakage Dominant Technologies
    Man L Mui, K. Banerjee and A. Mehrotra
  11. A Comprehensive Analytical Capacitance Model of a Two Dimensional Nanodot Array
    A. Basu, S-C. Lin, C. Wasshuber, A. Ionescu and K. Banerjee
  12. A Global Interconnect Optimization Scheme for Nanometer Scale VLSI with Implications for Latency, Bandwidth and Power Dissipation
    Man Lung Mui, Kaustav Banerjee and Amit Mehrotra

2003

  1. 3D ICs DSM Interconnect Performance Modeling and Analysis
    S. Souri, T-Y. Chiang, P. Kapur, K. Banerjee and K. C. Saraswat
    in Interconnect Technology and Design for Gigascale Integration, Editors: Jeffrey A. Davis and James D. Meindl, Springer, ISBN: 1-4020-7606-1, 2003
  2. A Self-Consistent Junction Temperature Estimation Methodology for Nanometer Scale ICs with Implications for Performance and Thermal Management
    K. Banerjee, S-C. Lin, A. Keshavarzi, S. Narendra and V. De
  3. SETMOS: A Novel True Hybrid SET-CMOS High Current Coulomb Blockade Oscillation Cell for Future Nano-Scale Analog ICs
    S. Mahapatra, V. Pott, S. Ecoffey, A. Schmid, C. Wasshuber, J. W. Tringe, Y. Leblebici, M. Declercq, K. Banerjee and A. M. Ionescu
  4. Nano, Quantum, and Molecular Computing: Are we Ready for the Validation and Test Challenges?
    S. K. Shukla, R. Karri, S. C. Goldstein, F. Brewer, K. Banerjee, and S. Basu
    INVITED
  5. A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits
    S. Mahapatra, K. Banerjee, F. Pegeon, and A. M. Ionescu
  6. Nanometer Scale Issues for On-Chip Interconnections
    K. Banerjee
    IUMRS-ICAM, Symposium B-1, Si-LSI-Related Materials, Processes and Characterization Technology, Yokohama, Japan, October 8-13, 2003
    INVITED
  7. Thermal Issues in Designing Nanometer Scale Interconnects
    K. Banerjee
    20th International VLSI Multilevel Interconnection Conference (VMIC), Marina Del Rey, CA, September 22-25, 2003
    INVITED
  8. A SET Quantizer Circuit Aiming at Digital Communication System
    S. Mahapatra, A. M. Ionescu, K. Banerjee and M. J. Declercq
  9. Teaching Microelectronics in the Silicon ICs Showstopper Zone: A Course on Ultimate Devices and Circuits: Towards Quantum Electronics
    A. M. Ionescu, M. J. Declercq, K. Banerjee and S. Mahapatra
    4th European Workshop on Microelectronics Education (EWME), Baiona, Mancomunidad de Vigo, Spain, May 23-24, 2003 []
  10. An Interconnect Scaling Scheme with Constant On-Chip Inductive Effects
    Kaustav Banerjee and Amit Mehrotra
  11. Modeling of Temperature Dependent Contact Resistance for Analysis of ESD Reliability
    K-H. Oh, J-H. Chun, K. Banerjee, C. Duvvury, and R. W. Dutton
  12. Analysis of IR-Drop Scaling with Implications for Deep Submicron P/G Network Designs
    A. H. Ajami, K. Banerjee, A. Mehrotra and M. Pedram

2002

  1. Via Design and Scaling Strategy for Nanometer Scale Interconnect Technologies
    S. Im, K. Banerjee and K. E. Goodson
  2. Non-uniform Conduction Induced Reverse Channel Length Dependence of ESD Reliability for Silicided NMOS Transistors
    K-H. Oh, K. Banerjee, C. Duvvury and R. W. Dutton
  3. Modeling and Analysis of Power Dissipation in Single Electron Logic
    S. Mahapatra, A. M. Ionescu, K. Banerjee and M. J. Declercq
  4. Impact of Gate-to-Contact Spacing on ESD Performance of Salicided Deep Submicron NMOS Transistors
    Kwang-Hoon Oh, Charvaka Duvvury, Kaustav Banerjee and Robert W. Dutton
  5. Analysis of Nonuniform ESD Current Distribution in Deep Submicron NMOS Transistors
    Kwang-Hoon Oh, Charvaka Duvvury, Kaustav Banerjee and Robert W. Dutton
  6. Analysis and Optimization of Substrate Noise Coupling in Single-Chip RF Transceiver Design
    A. Koukab, K. Banerjee, and M. Declercq
  7. A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs
    Kaustav Banerjee and Amit Mehrotra
  8. Quasi-Analytical Modeling of Drain Current and Conductance of Single Electron Transistors with MIB
    S. Mahapatra, A. M. Ionescu and K. Banerjee
  9. Analysis of On-Chip Inductance Effects for Distributed RLC Interconnects
    Kaustav Banerjee and Amit Mehrotra
  10. Analysis and Design of Distributed ESD Protection Circuits for High-Speed Mixed-Signal and RF ICs
    Choshu Ito, Kaustav Banerjee and Robert W. Dutton
  11. Power Dissipation Issues in Interconnect Performance Optimization for Sub-180 nm Designs
    K. Banerjee and A. Mehrotra
  12. Few Electron Devices: Towards Hybrid CMOS-SET Integrated Circuits
    M. Ionescu, M. J. Declercq, S. Mahapatra, K. Banerjee and J. Gautier
    INVITED
  13. Analysis of Gate-Bias-Induced Heating Effects in Deep-Submicron ESD Protection Designs
    Kwang-Hoon Oh, Charvaka Duvvury, Kaustav Banerjee and Robert W. Dutton
  14. A Quasi-Analytical SET Model for Few Electron Circuit Simulation
    Santanu Mahapatra, Adrian Mihai Ionescu and Kaustav Banerjee
  15. SET-based Quantiser Circuit for Digital Communications
    Santanu Mahapatra, Adrian Mihai Ionescu, Kaustav Banerjee and Michel Declercq
  16. Investigation of Gate to Contact Spacing Effect on ESD Robustness of Salicided Deep Submicron Single Finger NMOS Transistors
    K-H. Oh, C. Duvvury, K. Banerjee and R. W. Dutton
  17. Modeling and Analysis of Via Hot Spots and Implications for ULSI Interconnect Reliability
    S. Im, K. Banerjee and K. E. Goodson
  18. Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET (SG-MOSFET) with a Metal Over-Gate-Architecture
    A. M. Ionescu, V. Pott, R. Fritschi, K. Banerjee, M. J. Declercq, Ph. Renaud, C. Hibert, Ph. Fluckiger and G-A. Racine
  19. Inductance Aware Interconnect Scaling
    Inductance Aware Interconnect Scaling
  20. 3-D Integrable Optoelectronic Devices for Telecommunications ICs
    P. Dainesi, A. M. Ionescu, L. Thevenaz, K. Banerjee, M. J. Declercq, Ph. Robert, Ph. Renaud, Ph. Fluckiger, C. Hibert and G-A. Racine
  21. Analytical Thermal Model for Multilevel VLSI Interconnects Incorporating Via Effect
    Ting-Yen Chiang, Kaustav Banerjee and Krishna C. Saraswat

2001

  1. Gate Bias Induced Heating Effect and Implications for the Design of Deep Submicron ESD Protection
    K-H. Oh, C. Duvvury, K. Banerjee and R. W. Dutton
  2. Localized Heating Effects and Scaling of Sub-0.18 Micron CMOS Devices
    E. Pop, K. Banerjee, P. Sverdrup, R. Dutton and K. Goodson
  3. Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion
    A. H. Ajami, K. Banerjee and M. Pedram
  4. Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets
    K. Banerjee and A. Mehrotra
  5. Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects
    T-Y. Chiang, K. Banerjee and K. C. Saraswat
  6. Analysis and Optimization of Distributed ESD Protection Circuits for High-Speed Mixed Signal and RF Applications
    C. Ito, K. Banerjee and R. W. Dutton
  7. Interconnect Reliability under ESD Conditions: Physics, Models and Design Guidelines
    K. Banerjee
    23rd Annual EOS/ESD Symposium, pp. 191, Portland, Oregon, September 9-13, 2001 []
  8. Global (Interconnect) Warming
    Kuastav Banerjee and Amit Mehrotra
    INVITED
  9. Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs
    A. H. Ajami, K. Banerjee, M. Pedram, and L.P.P.P. van Ginneken
  10. Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology RT-Distributed RLC Interconnects
    K. Banerjee and A. Mehrotra
    BEST PAPER AWARD
  11. Accurate Analysis of On-Chip Inductance Effects and Implications for Optimal Repeater Insertion and Technology Scaling
    K. Banerjee and A. Mehrotra
  12. Non-Uniform Chip-Temperature Dependent Signal Integrity
    A. H. Ajami, K. Banerjee and M. Pedram
  13. A New Analytical Thermal Model for Multilevel VLSI Interconnects Incorporating Via Effects
    T-Y Chiang, K. Banerjee and K. C. Saraswat
  14. RF LDMOS Characterization and Its Compact Modeling
    J. Jang, O. Tornblad, T. Arnborg, Q. Chen, K. Banerjee, Z. Yu and R. W. Dutton
  15. 3-D Heterogeneous ICs: A Technology for the Next Decade and Beyond
    K. Banerjee, S. J. Souri, P. Kapur and K. C. Saraswat
    5th IEEE Workshop on Signal Propagation on Interconnects, Venice, Italy, May 13-16, 2001 []
  16. A Fast Analytical Technique for Estimating the Bounds of On-Chip Clock Wire Inductance
    Y-C. Lu, K. Banerjee, M. Celik and R. W. Dutton
  17. Effects of Non-Uniform Substrate Temperature on the Clock Signal Integrity in High Performance Designs
    A. H. Ajami, M. Pedrarn and K. Banerjee
  18. 3-D ICs: A Novel Chip Design for Improving Deep Submicrometer Interconnect Performance and Systems-on-Chip Integration
    Kaustav Banerjee, Shukri J. Souri, Pawan Kapur, and Krishna C. Saraswat
    INVITED
  19. Non-uniform Bipolar Conduction in Single Finger NMOS Transistors and Implications for Deep Submicron ESD Design
    K-H. Oh, C. Duvvury, C. Salling, K. Banerjee, and R. W. Dutton
  20. Analysis and Optimization of Thermal Issues in High-Performance VLSI
    K. Banerjee, M. Pedram and A. H. Ajami
    INVITED
  21. Analysis and Design of ESD Protection Circuits for High-Frequency/RF Applications
    C. Ito, K. Banerjee and R. W. Dutton
  22. Trends for ULSI Interconnections and Their Implications for Thermal, Reliability and Performance Issues
    K. Banerjee
    Seventh International Dielectrics and Conductors for ULSI Multilevel Interconnection Conference (DCMIC), pp. 38-50, Santa Clara, CA, March 5-9, 2001 []
    INVITED
  23. Interconnect Limits on Gigascale Integration (GSI) in the 21st Century
    Jeffrey A. Davis, Raguraman Venkatesan, Alain Kaloyeros, Michael Beylansky, Shukri J. Souri, Kaustav Banerjee, Krishna C. Saraswat, Arifur Rahman, Rafael Reif, and James. D. Meindl
    Proceedings of the IEEE, Special Issue on Limits of Semiconductor Technology, Vol. 89, No. 3, pp. 305- 324, March 2001 []
    INVITED

2000

  1. Full Chip Thermal Analysis of Planar (2-D) and Vertically Integrated (3-D) High Performance ICs
    S. Im and K. Banerjee
  2. Effect of Via Separation and Low-k Dielectric Materials on the Thermal Characteristics of Cu Interconnects
    T-Y. Chiang, K. Banerjee, K. C. Saraswat
  3. Thermal Effects in ULSI Interconnects
    K. Banerjee
    Fabless Semiconductor Association (FSA) Design Modeling Workshop, Santa Clara, CA, Oct. 11-12, 2000
    INVITED TUTORIAL
  4. Advanced Electro-Thermal Modeling and Simulation Techniques for Deep Sub-Micron Devices
    P. G. Sverdrup, O. Tornblad, K. Banerjee, D. Yergeau, Z. Yu, R. W. Dutton, and K. E. Goodson
    Proceedings of TECHCON, Phoenix, AZ, Sept. 21-23, 2000
  5. 3-D ICs: Motivation, Performance Analysis, and Technology
    K. C. Saraswat, K. Banerjee, A. R. Joshi, P. Kalavade, P. Kapur, and S. J. Souri
    Proc. 26th European Solid-State Circuits Conference (ESSCIRC &lsquo;2000), Stockholm, Sweden, Sept. 19 - 21, 2000
    INVITED
  6. Sub-Continuum Thermal Simulations of Deep Sub-micron Devices under ESD Conditions
    P. G. Sverdrup, K. Banerjee, C. Dai, W. Shih, R. W. Dutton, and K. E. Goodson
  7. Multiple Si Layer ICs: Motivation, Performance Analysis, and Design Implications
    S. J. Souri, K. Banerjee, A. Mehrotra, and K. C. Saraswat
  8. 3-D lCs with Multiple Si Layers: Performance Analysis, and Technology
    K. C. Saraswat, K. Banerjee, A. Joshi. P. Kalavade, S. J. Souri, and V. Subramanian
    197th Meeting of The Electrochemical Society, Toronto, May 14-18, 2000
    INVITED
  9. Thermal Characteristics of Sub-Micron Vias Studied by Scanning Joule Expansion Microscopy
    Masanobu Igeta, Kaustav Banerjee, Guanghua Wu, Chenming Hu, and Arun Majumdar
  10. Microanalysis of VLSI Interconnect Failure Modes under Short-pulse Stress Conditions
    K. Banerjee, D. Y. Kim, A. Amerasekera, C. Hu, S. S. Wong, and K. E. Goodson
  11. Quantitative Projections of Reliability and Performance for Low-k/Cu Interconnect Systems
    K. Banerjee, A. Mehrotra, W. Hunter, K. C. Saraswat, K. E. Goodson, and S. S. Wong
  12. Process and Layout Dependent Substrate Resistance Modeling for Deep Sub-Micron ESD Protection Devices
    X. Y. Zhang, K. Banerjee, A. Amerasekera, V. Gupta, Z. Yu, and R. W. Dutton
  13. Performance Analysis and Technology of 3-D ICs
    K. C. Saraswat, S. J. Souri, K. Banerjee, P. Kapur
    ACM International Workshop on System Level Interconnect Prediction (SLIP), pp. 85-90, San Diego, CA, April 8-9, 2000
    INVITED
  14. Thermal Effects in Deep Sub-Micron VLSI Interconnects
    Kaustav Banerjee
    IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 20-22, 2000
    INVITED TUTORIAL

1999

  1. Thermal Effects in Deep Sub-micron VLSI Interconnects and Implications for Reliability and Performance
    Kaustav Banerjee
    Electronics Research Laboratory, Memorandum no. UCB/ERL M99/48, September 22, 1999
  2. On Thermal Effects in Deep Sub-Micron VLSI Interconnects
    K. Banerjee, A. Mehrotra, A. Sangiovanni-Vincentelli, and C. Hu
  3. Investigation of Self-Heating Phenomenon in Small Geometry Vias Using Scanning Joule-Expansion Microscopy
    K. Banerjee, G. Wu, M. Igeta, A. Amerasekera, A. Majumdar, and C. Hu

1998

  1. Comparison of E and 1/E TDDB Model for Si02 under Long-Term/Low-Field Test Conditions
    J.W. McPherson, V. Reddy, K. Banerjee, and H. Le
  2. A New Quantitative Model for Deep Submicron Contact Resistance
    K. Banerjee, A. Amerasekara, G. Dixit, and C. Hu
    Proceedings of the TECHON, Las Vegas, NV, 1998
  3. High Current Effects in Silicide films for Sub-0.25 micron VLSI Technologies
    K. Banerjee, A. Amerasekera, J. A. Kittl, and C. Hu
  4. Thermal Effects in Interconnects
    W. Hunter, W-Y. Shih and K. Banerjee
    IEEE Annual International Reliability Physics Symposium (IRPS), Reno, NV, March 30 - April 2, 1998
    INVITED TUTORIAL
  5. Characterization of Self-Heating in Advanced VLSI Interconnect Lines Based on Thermal Finite Element Simulation
    Sven Rzepka, Kaustav Banerjee, Ekkehard Meusel, and Chenming Hu

1997

  1. Temperature and Current Effects on Small-Geometry-Contact Resistance
    K. Banerjee, A. Amerasekera, G. Dixit, and C. Hu
  2. High Current Effects in Metal Interconnects
    K. Banerjee, A. Amerasekera, G. Dixit, and C. Hu
    Proceedings of the SRC Topical Research Conference on Reliability, Vanderbilt University, Nashville, Oct. 21-22, 1997
    INVITED
  3. Characterization of Self-Heating in Advanced VLSI Interconnect Lines Based on Thermal Finite Element Simulation
    S. Rzepka, K. Banerjee, E. Meusel, and C. Hu
    3rd International Workshop on Thermal Investigations of ICs and Microstructures (THERMINIC), pp. 108-113, Cannes / Cote d'Azur, France, Sept. 21-23, 1997
  4. High-Current Failure Model for VLSI Interconnects Under Short-PuIse Stress Conditions
    Kaustav Banerjee, Ajith Amerasekera, Nathan Cheung, and Chenming Hu
  5. Characterization of Contact and Via Failure under Short Duration High Pulsed Current Stress
    K. Banerjee, A. Amerasekera, G. Dixit, N. Cheung, and C. Hu
  6. Failure Mechanisms of Multi Layered Thin Film Metal Interconnects under a High Current Pulse
    K. Banerjee, A. Amerasekera, N. Cheung, and C. Hu
    MRS Spring Symp., San Francisco, CA, March 31-April 4, 1997

1996

  1. The Effect of Interconnect Scaling and Low-k Dielectric on the Thermal Characteristics of the IC Metal
    K. Banerjee, A. Amerasekera, G. Dixit, and C. Hu
  2. The Dependence of W-plug Via EM Performance on Via Size
    Huy A. Le, Kaustav Banerjee, and Joe W. McPherson
  3. Thermal Analysis of the Fusion Limits of Metal Interconnect under Short Duration Current Pulses
    K. Banerjee, S. Rzepka, A. Amerasekera, N. Cheung, and C. Hu
  4. Characterization and Simulation of Self Heating in a Multi Level VLSI Interconnect System under DC and Pulsed Current Conditions
    K. Banerjee, S. Rzepka, A. Amerasekera, and C. Hu
    Proceedings of the SRC TECHCON, Phoenix, AZ, Sept. 1996
  5. Impact of High Current Stress Conditions on VLSI Interconnect Electromigration Reliability Evaluation
    K. Banerjee, L. Ting, N. Cheung, and C. Hu
    Proceedings of the Thirteenth International VLSI Multilevel Interconnection Conference (VMIC), pp. 289- 294, Santa Clara, CA, June 18-20, 1996
  6. Characterization of VLSI Circuit Interconnect Heating and Failure under ESD Conditions
    K. Banerjee, A. Amerasekera, and C. Hu