We have highlighted an underlying physical concept behind the BTBT process that has been mostly overlooked in literature. It has been shown that ignoring the dual nature of electrons and holes during the BTBT phenomenon can not only lead to substantially erroneous results but also to misleading...
Significance of Electron-Hole Duality During Band-to-Band Tunneling Process for Designing Tunneling FETs
We have highlighted an underlying physical concept behind the BTBT process that has been mostly overlooked in literature. It has been shown that ignoring the dual nature of electrons and holes during the BTBT phenomenon can not only lead to substantially erroneous results but also to misleading conclusions. During the tunneling phenomenon, particles transit through a forbidden gap with imaginary wave-vectors. If only electron (hole) tunneling and thereby only the barrier for electrons (holes) are considered, it implies that the electron (hole) faces a barrier at the valence (conduction) band edge, and hence its wave-vector becomes imaginary there, which is unphysical because the wave-vector can be imaginary only within the bandgap and not on the valence/conduction band edge. Understanding the EHD concept is also vital for accurately determining the regime of validity of the WKB method and can thereby dispel criticisms that seem to have smeared its reputation. While all the results in this paper are presented for GNRs, the EHD concept is inherent to the physics of the BTBT process and hence is applicable to any other material.
Reference: D. Sarkar, M. Krall, and K. Banerjee, "Electron-hole Duality During Band-to-Band Tunneling Process in Graphene-Nanoribbon Tunnel-Field-Effect Transistors," Applied Physics Letters, 97, No. 26, p. 263109, Dec 27, 2010.
Laterally-Actuated Nano-Electro-Mechanical Switches Can Lead to Ultra-Energy-Efficient and Compact Logic Gates
We have reported the fabrication and modeling of laterally-actuated double-electrode NEMS structures and design of novel logic gates using such devices.Furthermore, novel NEMS-based inverter, NAND, NOR and XOR gates are proposed. It is shown that an XOR gates can be implemented using only two NEMS devices and hence, it is possible to develop ultra compact NEMS-based arithmetic units. The proposed NEMS device and logic gates can potentially lead to unprecedented levels of energyefficiency in digital IC design. More interestingly, it is shown that the availability of such compact XOR/XNOR gates has profound implications for simplifying Boolean functions using Karnaugh maps (K-maps). It is shown that he diagonal grouping of adjacent “1s” in a K-map is also possible as a result of the availability of the proposed compact XOR/XNOR gates. This enables circuit designers to implement energy-efficient logic functions using significantly fewer transistors.
References: H.F. Dadgour, M.M. Hussain and K. Banerjee, "A New Paradigm in the Design of Energy-Efficient Digital Circuits Using Laterally-Actuated Double-Gate NEMS," IEEE International Symposium on Low Power Electronics and Design (ISLPED), Austin, TX, August 18-20, pp. 7-12, 2010.
H. F. Dadgour, M. M. Hussain, C. Smith and K. Banerjee, "Design and Analysis of Compact Ultra Energy-Efficient Logic Gates Using Laterally-Actuated Double-Electrode NEMS," Design Automation Conference (DAC), Anaheim, CA, June 13-18, 2010, pp. 893-896.
Accurate electrostatic and high-frequency models for TSVs have been developed in NRL. It is shown that the MOS effect, or the depletion region surrounding the TSV isolation dielectric must be considered for accurate AC analysis. The model can be used to analyze the performance of TSVs made of various materials, including carbon nanotubes.
Reference: Chuan Xu, Hong Li, Roberto Suaya, and Kaustav Banerjee,"Compact AC Modeling and Analysis of Cu, W, and CNT based Through-Silicon Vias (TSVs) in 3-D ICs," IEEE International Electron Device Meeting (IEDM) 2009, pp.521-524.
Carbon nanotube (CNT) bundle based interconnects have been shown to possess unique high-frequency properties: they exhibit significantly lesser skin effect compared to conventional metals. This has significant implications for high-frequency/RF circuit design. The Figure shows that CNT based on-chip planar inductors could provide more than 3 times higher Q-factor than conventional Cu based inductors.
Reference: Hong Li and Kaustav Banerjee, “High-Frequency Analysis of Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design,” IEEE Transactions on Electron Devices, Vol. 56, No. 10, pp. 2202-2214, Oct. 2009.
Work-Function Variation Identified as a New Source of Random Threshold Voltage Fluctuation in Emerging Metal-Gate Transistors
The work function, or the minimum energy to remove an electron from a solid surface, depends on a combination of the chemical potential of the bulk material plus a surface dipole potential, which is a function of the orientation of metal grains within the gate. This introduces a new source of random variability in the transistor's threshold voltage. NRL researchers (in collaboration with AIST-Japan and Intel) have also developed modeling and analytical techniques for predicting this work-function variation for different metal compounds, helping process designers to tune their metal-gate technologies, device designers to predict and minimize threshold voltage variations, and circuit designers to optimize their designs to minimize the impact of this variation.
Reference: H. Dadgour, K. Endo, V. De and K. Banerjee, "Modeling and Analysis of Grain-Orientation Effects in Emerging Metal-Gate Devices and Implications for SRAM Reliability," IEEE International Electron Devices Meeting (IEDM), pp. 705-708, San Francisco, Dec. 15-17, 2008
Sheng-Chih Lin, research highlighted on the cover of the Jan. 2008 "IEEE Transactions on Electron Devices" journal - the journal cover image shows a self-consistent simulation of the temperature profile of a modern silicon integrated circuit adapted from the paper titled ‘‘Cool Chips: Opportunities and Implications for Power and Thermal Management’’ by S-C Lin and K. Banerjee, published in the same issue. Lin's doctoral work was on thermal management of nanoscale integrated circuits. He worked with Prof. Kaustav Banerjee and graduated in Dec. 2007.. He is now on the Technical Staff at Intel Corp.