We have highlighted an underlying physical concept behind the BTBT process that has been mostly overlooked in literature. It has been shown that ignoring the dual nature of electrons and holes during the BTBT phenomenon can not only lead to substantially erroneous results but also to misleading...
We have reported the fabrication and modeling of laterally-actuated double-electrode NEMS structures and design of novel logic gates using such devices.Furthermore, novel NEMS-based inverter, NAND, NOR and XOR gates are proposed. It is shown that an XOR gates can be implemented using only two NEMS devices and hence, it is possible to develop ultra compact NEMS-based arithmetic units. The proposed NEMS device and logic gates can potentially lead to unprecedented levels of energyefficiency in digital IC design. More interestingly, it is shown that the availability of such compact XOR/XNOR gates has profound implications for simplifying Boolean functions using Karnaugh maps (K-maps). It is shown that he diagonal grouping of adjacent “1s” in a K-map is also possible as a result of the availability of the proposed compact XOR/XNOR gates. This enables circuit designers to implement energy-efficient logic functions using significantly fewer transistors.
References: H.F. Dadgour, M.M. Hussain and K. Banerjee, "A New Paradigm in the Design of Energy-Efficient Digital Circuits Using Laterally-Actuated Double-Gate NEMS," IEEE International Symposium on Low Power Electronics and Design (ISLPED), Austin, TX, August 18-20, pp. 7-12, 2010.
H. F. Dadgour, M. M. Hussain, C. Smith and K. Banerjee, "Design and Analysis of Compact Ultra Energy-Efficient Logic Gates Using Laterally-Actuated Double-Electrode NEMS," Design Automation Conference (DAC), Anaheim, CA, June 13-18, 2010, pp. 893-896.