Arnab Pal

 Arnab Pal was born in Siliguri, West Bengal, India. He received his M.Tech degree in Microelectronics from the Indian Institute of Technology (IIT) Kanpur, in 2015, where he was the recipient of an Academic Excellence Award. For his master's thesis, Arnab developed an analytical model of the drain current characteristics of tunnel-FETs that captured several intricate physics and is chronicled in an article published in the IEEE Transactions on Electron Devices. Earlier, he received his B.Tech degree in Electronics and Communication Engineering from Kalyani Government Engineering College (WBUT), Kalyani, in 2013. During 2015-2016 he worked at Intel India as a Digital Design Engineer with the Microprocessor Big Core Team, where his responsibilities included the design of high-performance microprocessors based on a cutting-edge CMOS technology node, and his work received recognition from Intel. In Fall 2016, he joined Prof. Banerjee's Nanoelectronics group at the University of California, Santa Barbara, to pursue his Ph.D. degree. His current research is focused on exploring novel techniques for improving the energy-efficiency and performance of nano-devices based on 2D materials.  (2023 - Intel)