Publications

2024

• Three-dimensional Transistors with Two-dimensional Semiconductors for Future CMOS Scaling
  Arnab Pal, Tanmay Chavan, Jacob Jabbour, Wei Cao and Kaustav Banerjee
  Nature Electronics, Vol. 7, pp. 1147-1157, Dec 16, 2024.
  News & Views: What's next for FETs?

• A Framework for Exploring Gate-Dielectric Materials for High-Performance Two-Dimensional Field-Effect-Transistors
  Ankit Kumar, Lin Xu, Albert Ho, Arnab Pal, Kunjesh Agashiwala, Kamyar Parto, Wei Cao and Kaustav Banerjee
  IEEE Transactions on Materials for Electron Devices, Vol. 1, pp. 211-220, Dec 9, 2024.

• Analysis and Implication of Electrothermal Effects in Emerging 3D Transistors and Integration Topologies with Two-dimensional Semiconductors
  L. Xu, A. Kumar, E. Quezada, J. Jiang, G. Oh, K. Agashiwala, J. Jiang, A. Pal, W. Cao, M. Lee and K. Banerjee
  IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, December 7-11, 2024, pp. 32.2.1-32.2.4.

• Exploration and Analysis of Metallic, Optical, and Superconducting Cryo-Interconnects for Large-Scale Quantum Computers
  A. Kumar, A. Kim, K. Agashiwala, L. Xu, A. Pal, W. Cao, and K. Banerjee
  IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, December 7-11, 2024, pp. 26.2.1-26.2.4.

• Strain Engineering in 2D FETs: Physics, Status, and Prospects
  Ankit Kumar, Lin Xu, Arnab Pal, Kunjesh Agashiwala, Kamyar Parto, Wei Cao, and Kaustav Banerjee
  Journal of Applied Physics 136, 090901, 2024.
  Included in the Special Collection of Journal of Applied Physics
  Highlighted by SemiEngineering

• Roadmap on Printable Electronic Materials for Next-generation Sensors
  Vincenzo Pecunia, et al., (Section 8.5: Printable FET biosensors based on 2D materials, A. Pal and K. Banerjee)
  Nano Futures 8 (3), 032001, 2024.

• An Ultra Energy-efficient Hardware Platform for Neuromorphic Computing Enabled by 2D-TMD Tunnel-FETs
  Arnab Pal, Zichun Chai, Junkai Jiang, Wei Cao, Mike Davies, Vivek De, and Kaustav Banerjee
  Nature Communications 15 (1), 3392, 2024.
  Highlighted by National Academy of Engineering (NAE) Frontiers of Engineering
  Read Media Coverage by UCSB Current

• Transistors à effet de champ à capacité négative
  Wei Cao et Kaustav Banerjee
  Au-delà du CMOS (Ed. A. Cresti), ISTE Group, 2024.

• Cmos-compatible graphene structures, interconnects and fabrication methods
  K. Banerjee, J. Jiang, K. Agashiwala
  US Patent App. 18/252,459, Jan 11, 2024.

2023

• A Materials-Device Co-Design Framework for Realizing Ultra Energy-Efficient All-2D Spin-Logic Circuits with 2D-Materials
  S. Zhang*, A. Pal*, W. Yin, W. Cao and K. Banerjee (*equal contribution)
  IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, December 9-13, 2023, pp. 3.4.1-3.4.4.
  Highlighted Paper among the 18 Most Significant Papers
  Highlighted by the IEEE Electron Devices Society

• Advancing High-Performance Large-Scale Quantum Computing with Cryogenic 2D-CMOS
  K. Agashiwala, A. Pal, H. Cui, T. Chavan, W. Cao and K. Banerjee
  IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, December 9-13, 2023, pp. 3.3.1-3.3.4.
  Outstanding Student Paper

• The Future Transistors
  Wei Cao, Huiming Bu, Maud Vinet, Min Cao, Shinichi Takagi, Sungwoo Hwang, Tahir Ghani, and Kaustav Banerjee
  Nature 620 (7974), 501–515, 2023.

• Negative Capacitance Field-Effect Transistors
  W. Cao and K. Banerjee
  Chapter 3 in Beyond‐CMOS: State of the Art and Trends, Ed: A. Cresti, John Wiley & Sons Inc., Print ISBN:9781789451276, ;pp. 79-107, July 21, 2023.

• Quantum-Engineered Devices Based on 2D Materials for Next-Generation Information Processing and Storage
  Arnab Pal, Shuo Zhang, Tanmay Chavan, Kunjesh Agashiwala, Chao-Hui Yeh, Wei Cao, and Kaustav Banerjee
  Advanced Materials, Special Issue: Quantum Materials, Vol. 35, Issue 27, 2109894, July 6, 2023.
  Included in a collection of Advanced Quantum Technologies

• Exploration and Exploitation of Strain Engineering in 2D-FETs
  A. Kumar, A. Pal, K. Parto, W. Cao, and K. Banerjee
  Device Research Conference (DRC), Santa Barbara, CA, June 25-28, 2023, p. 1-2

• Hybrid Transistor and Memory Cell
  K. Banerjee, C-H. Yeh, W. Cao, A. Pal
  US Patent App. 17/965,099, April 4, 2023

2022

• Characterization and Closed Form Modeling of Edge/Top/Hybrid Metal-2D Semiconductor Contacts
  A. Pal, V. Mishra, J. Weber, K. Krishnaswamy, K. Ghosh, A. V. Penumatcha, S. Berrada, K. O’Brien, D. Kencke, and K. Banerjee
  IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, December 3-7, 2022, pp. 28.5.1-28.5.4.
  Highlighted by Intel's talk at IEDM 2022 (Read Media Coverage by Newsbreak)

2021

• Two-Dimensional Materials Enabled Next-Generation Low-Energy Compute and Connectivity
  Arnab Pal, Kunjesh Agashiwala, Junkai Jiang, Dujiao Zhang, Tanmay Chavan, Ankit Kumar, Chao-Hui Yeh, Wei Cao, and Kaustav Banerjee
  MRS Bulletin 46, 211–1228, Dec 2021.
  Included in the special issue of MRS Bulletin

• Sustaining Moore’s Law with Graphene
  Kunjesh Agashiwala, Junkai Jiang, Ankit Kumar, Chao-Hui Yeh, and Kaustav Banerjee
  Chip Scale Review, pp. 26-35, Nov-Dec 2021.
  Cover Page Recognition &amp Featured Article

• One-Dimensional Edge Contacts to Two-Dimensional Transition-Metal Dichalcogenides: Uncovering the Role of Schottky-Barrier Anisotropy in Charge Transport across MoS2/Metal Interfaces
  Kamyar Parto, Arnab Pal, Tanmay Chavan, Kunjesh Agashiwala, Chao-Hui Yeh, Wei Cao, and Kaustav Banerjee
  Phys. Rev. Applied 15, 064068, 28 June 2021.
  Included in the collection of Physical Review Applied

• Defect and Strain Engineering of Monolayer WSe2 Enables Site Controlled Single-Photon Emission up to 150 K
  Kamyar Parto, Shaimaa I. Azzam, Kaustav Banerjee, and Galan Moody
  Nature Communications, 12, 3585, June 11, 2021.

• Demonstration of CMOS-Compatible Multi-Level Graphene Interconnects With Metal Vias
  Kunjesh Agashiwala*, Junkai Jiang*, Kamyar Parto, Dujiao Zhang, Chao-Hui Yeh, and Kaustav Banerjee (*equal contribution)
  IEEE Transactions on Electron Devices, Vol. 68, No. 4, pp. 2083-2091, Apr. 2021
  Included in a Selection of Extended Versions of Outstanding Student Papers Presented at IEDM 2020

• 0.5T0.5R—An Ultracompact RRAM Cell Uniquely Enabled by van der Waals Heterostructures
  Dujiao Zhang*, Chao-Hui Yeh*, Wei Cao, and Kaustav Banerjee (*equal contribution)
  IEEE Transactions on Electron Devices, Vol. 68, No. 4, pp. 2033-2040, Apr. 2021.
  Included in a Selection of Extended Versions of Outstanding Student Papers Presented at IEDM 2020
  Highlighted by Research Highlights of Nature Electronics, 4, page 321, May 25, 2021.

• A Mode-Balanced Reconfigurable Logic Gate Built in a van der Waals Strata
  Wei Cao, Jae Hwan Chu, Kamyar Parto and Kaustav Banerjee
  npj 2D Materials and Applications, 5, 20, pp. 1-7, Feb. 2021.

2020

• Reliability and Performance of CMOS-Compatible Multi-Level Graphene Interconnects Incorporating Vias
  Kunjesh Agashiwala*, Junkai Jiang*, Chao-Hui Yeh, Kamyar Parto, Dujiao Zhang, and Kaustav Banerjee (*equal contribution)
  IEEE International Electron Devices Meeting (IEDM), Virtual, December 12-18, 2020, pp. 31.1.1-31.1.4.
  Outstanding Student Paper - Invited to a Special Issue in IEEE T-ED
  Highlighted Paper - IEDM 2020 Editor Press

• 0.5T0.5R - Introducing an Ultra-Compact Memory Cell Enabled by Shared Graphene Edge-Contact and h-BN Insulator
  Chao-Hui Yeh*, Dujiao Zhang*, Wei Cao, and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), Virtual, December 12-18, 2020, pp. 12.3.1-12.3.4. (*equal contribution)
  Outstanding Student Paper - Invited to a Special Issue in IEEE T-ED

• A Compact Current-Voltage Model for 2-D-Semiconductor-Based Lateral Homo-/Hetero-Junction Tunnel-FETs
  Arnab Pal, Wei Cao and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Vol. 67, No. 10, pp. 4473-4481, Oct. 2020.

• Irradiation of Nanostrained Monolayer WSe₂ for Site-Controlled Single-Photon Emission up to 150K
  Kamyar Parto, Kaustav Banerjee, and Galan Moody
  Frontiers in Optics Laser Science (FIOLS), Sept. 14-17, 2020.

• Impact of Transport Anisotropy on the Performance of van der Waals Materials-Based Electron Devices
  Wei Cao, Mengqi Huang, Chao-Hui Yeh, Kamyar Parto, and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Vol. 67, No. 3, pp. 1310-1316, Mar. 2020.

• Is Negative Capacitance FET a Steep-slope Logic Switch?
  Wei Cao and Kaustav Banerjee
  Nature Communications, 11, 196, pp. 1-8, January 10, 2020.
  Selected in Research Highlights of Nature Electronics, Feb 24, 2020
  Read Media Coverage by Building An Ideal MOSFET

• Correction to “Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability”
  Chuan Xu, Seshadri K Kolluri, Kazhuhiko Endo, and Kaustav Banerjee
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 39, No. 1, pp. 277-277, January 2020.

2019

• Computational Study of Spin Injection in 2D Materials
  Arnab Pal, Kamyar Parto, Kunjesh Agashiwala, Wei Cao, and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), San Francisco, December 7-11, 2019, pp. 24.2.1-24.2.4.

• Area-Selective-CVD Technology Enabled Top-Gated and Scalable 2D-Heterojunction Transistors with Dynamically Tunable Schottky Barrier
  Chao-Hui Yeh, Wei Cao, Arnab Pal, Kamyar Parto, and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), San Francisco, December 7-11, 2019, pp. 23.4.1-23.4.4.

• Ultimate Monolithic-3D Integration With 2D Materials: Rationale, Prospects, and Challenges
  Junkai Jiang, Kamyar Parto, Wei Cao, and Kaustav Banerjee
  IEEE Journal of the Electron Devices Society, Vol. 7, pp. 878-887, 2019.
  Special Section on the 2018 IEEE S3S Conference
  Read Media Coverage by UCSB Current, Polyscope E-paper (Swiss Trade Magazine)

• Normally-Off Sputtered-MoS2 nMISFETs with MoSi2 Contact by Sulfur Powder Annealing and ALD Al2O3 Gate Dielectric for Chip Level Integration
  K. Matsuura, M. Hamada, T. Hamada, H. Tanigawa, T. Sakamoto, W. Cao, K. Parto, A. Hori, I. Muneta, T. Kawanago, K. Kakushima, K. Tsutsui, A. Ogura, K. Banerjee, and H. Wakabayashi
  19th IEEE International Workshop on Junction Technology (IWJT), June 6-7, Kyoto, Japan, 2019.

• Cryogenic Micro-PL of Monolayer 1T/2H MoS2 Superlattice
  Zhangji Zhao, Ibrahim Sarpkaya, Xuejun Xie, Kaustav Banerjee, Han Htoon, and Chee Wei Wong
  IEEE Conference on Lasers and Electro-Optics (CLEO), May 5-10, San Jose, CA, 2019.

2018

• CMOS-Compatible Doped-Multilayer-Graphene Interconnects for Next-Generation VLSI
  Junkai Jiang, Jae Hwan Chu and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), San Francisco, December 1-5, 2018, pp. 34.5.1-34.5.4. 
  Highlighted by Research Highlights of Nature Electronics as one of the two selected IEDM 2018 papers

• Can Kinetic Inductance in Low-Dimensional Materials Enable a New Generation of RF-Electronics?
  Kunjesh Agashiwala, Arnab Pal, Wei Cao, Junkai Jiang and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), San Francisco, December 1-5, 2018, pp. 24.4.1-24.4.4.

• Interfacial Thermal Conductivity of 2D Layered Materials: An Atomistic Approach
  Kamyar Parto, Arnab Pal, Xuejun Xie, Wei Cao and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), San Francisco, December 1-5, 2018, pp. 24.1.1-24.1.4.

• Monolithic-3D Integration with 2D Materials: Toward Ultimate Vertically-Scaled 3D-ICs
  Junkai Jiang, Kamyar Parto, Wei Cao and Kaustav Banerjee
  Proceedings of the IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), San Francisco, CA, Oct. 15-18, 2018, pp. 19.2.1–19.2.3.
  Best Student Paper Award

• 2-D Layered Materials for Next-Generation Electronics: Opportunities and Challenges
  Wei Cao, Junkai Jiang, Xuejun Xie, Arnab Pal, Jae-Hwan Chu, Jiahao Kang and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Vol. 65, No. 10, pp. 4109-4121, Oct. 2018.
  Invited in Special Issue on 2-D Materials for Electronic, Optoelectronic, and Sensor Devices

• 2D Materials for Smart Life
  Kaustav Banerjee
  IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM), Kobe, Japan, March 13-16, 2018, pp. 4-6.
  Plenary Paper

• On-Chip Intercalated-Graphene Inductors for Next-Generation Radio Frequency Electronics
  Jiahao Kang, Yuji Matsumoto, Xiang Li, Junkai Jiang, Xuejun Xie, Keisuke Kawamoto, Munehiro Kenmoku, Jae Hwan Chu, Wei Liu, Junfa Mao, Kazuyoshi Ueno and Kaustav Banerjee
  Nature Electronics, Vol. 1, No. 1, pp. 46-51, 2018.
  Read Media Coverage by Forbes

2017

• How to Derive the Highest Mobility from 2D FETs – A First-Principle Study
  Arnab Pal, Wei Cao, Jiahao Kang and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), San Francisco, December 2-6, 2017, pp. 31.3.1-31.3.4.

• Computational Study of Gate-Induced Drain Leakage in 2D-Semiconductor Field-Effect Transistors
  Jiahao Kang, Wei Cao, Arnab Pal, Sumeet Pandey, Steve Kramer, Richard Hill, Gurtej Sandhu and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), San Francisco, December 2-6, 2017, pp. 31.2.1-31.2.4.

• All-Carbon Interconnect Scheme Integrating Graphene-Wires and Carbon-Nanotube-Vias
  Junkai Jiang, Jiahao Kang, Jae Hwan Chu and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), San Francisco, December 2-6, 2017, pp. 14.3.1-14.3.4.
  Read Media Coverage by IEEE Spectrum

• Room Temperature 2D Memristive Transistor with Optical Short-Term Plasticity
  Xuejun Xie, Jiahao Kang, Yongji Gong, Pulickel M. Ajayan and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), San Francisco, December 2-6, 2017, pp. 5.3.1-5.3.4.
  Read Conference Report: IEDM - 2D Materials in Semiconductor-Today

• Designing Artificial 2D Crystals with Site and Size Controlled Quantum Dots
  Xuejun Xie, Jiahao Kang, Wei Cao, Jae Hwan Chu, Yongji Gong, Pulickel M. Ajayan and Kaustav Banerjee
  Scientific Reports, Vol. 7, No. 9965, 2017.
  Read Media Coverage by Phys.org and Science Daily among Scientific Report's Top 100 in Materials Science

• Boosting Hydrogen Evolution Performance of MoS₂ by Band Structure Engineering
  Jing Li*, Jiahao Kang*, Qian Cai, Wentin Hong, Chuanyong Jian, Wei Liu and Kaustav Banerjee (* Equal contributors)
  Advanced Materials Interfaces, Vol. 4, No. 16, p. 1700303, August 21, 2017.
  Read Media Coverage by Advanced Science News

• 2D/3D Tunnel-FET: Toward Green Transistors and Sensors
  Wei Cao, Jiahao Kang and Kaustav Banerjee
  ECS Transactions, Vol. 77, No. 5, 185-189, 2017.
  Invited Paper

• Characterization of Self-Heating and Current-Carrying Capacity of Intercalation Doped Graphene Nanoribbon Interconnects
  Junkai Jiang, Jiahao Kang and Kaustav Banerjee
  IEEE International Reliability Physics Symposium (IRPS), Monterey, April 4-6, 2017, pp. 6B.1.1-6B.1.6.

• Intercalation Doped Multilayer-Graphene-Nanoribbons for Next-Generation Interconnects
  Junkai Jiang, Jiahao Kang, Wei Cao, Xuejun Xie, Haojun Zhang, Jae Hwan Chu, Wei Liu and Kaustav Banerjee
  Nano Letters, Vol. 17, No. 3, pp. 1482-1488, 2017.
  Read Media Coverage by Nanotec (Thailand)

• 2D Materials for Next-Generation Ultra Energy-Efficient Electronics
  Kaustav Banerjee
  4th MUJU International Winter School Series, Muju Deogyusan Resort, Republic of Korea, Feb 5- 9, pp. 1-16, 2017.
  Invited

• Understanding the Device Physics in Polymer-Based Ionic-Organic Ratchets
  Yuanyuan Hu, Viktor Brus, Wei Cao, Kenneth Liao, Hung Phan, Ming Wang, Kaustav Banerjee, Guillermo C. Bazan and Thuc-Quyen Nguyen
  Advanced Materials, Vol. 29, No. 15, pp. 1606464, 2017.

2016

• Effect of Band-Tails on the Subthreshold Performance of 2D Tunnel-FETs
  Haojun Zhang, Wei Cao, Jiahao Kang and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), San Francisco, December 3-7, 2016, pp. 30.3.1-30.3.4.

• Prospects of Ultra-thin Nanowire Gated 2D-FETs for Next-Generation CMOS Technology
  Wei Cao, Wei Liu and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), San Francisco, December 3-7, 2016, pp. 14.7.1-14.7.4.

• An Ultra-Short Channel Monolayer MoS₂ FET Defined By the Curvature of a Thin Nanowire
  Wei Cao, Wei Liu, Jiahao Kang and Kaustav Banerjee
  IEEE Electron Device Letters, Vol. 37, No. 11, pp. 1497-1500, Nov. 2016.

• Two-Dimensional Van der Waals Materials
  Pulickel Ajayan, Philip Kim and Kaustav Banerjee
  Physics Today, Vol. 69, No. 9, pp. 38-44, 2016.
  Read Media Coverage by College of Engineering and ECE Department

• Characterization of FeCl₃ Intercalation Doped CVD Few-Layer Graphene
  Wei Liu, Jiahao Kang and Kaustav Banerjee
  IEEE Electron Device Letters, Vol. 37, No. 9, pp. 1246 - 1249, Sept. 2016.

• Undoped and Catalyst-Free Germanium Nanowires for High-Performance p-type Enhancement-Mode Field-Effect Transistors
  Marolop Simanullang, G. Bimananda M. Wisna, Koichi Usami, Wei Cao, Yukio Kawano, Kaustav Banerjee and Shunri Oda
  Journal of Materials Chemistry C, Vol. 4, No. 22, pp. 5102-5108, 2016.

• Electrical Characterization of Back-gated and Top-gated Germanium core/Silicon-shell Nanowire Field-effect Transistors
  M. Simanullang, G. B. M. Wisna, W. Cao, K. Usami, K. Banerjee, S. Oda
  IEEE Silicon Nanoelectronics Workshop (SNW), Honolulu, HI, 12-13 June 2016.

• Surface Functionalization of Two-dimensional Metal Chalcogenides by Lewis Acid-Base Chemistry
  Sidong Lei, Xifan Wang, Bo Li, Jiahao Kang, Yongmin He, Antony George, Liehui Ge, Yongji Gong, Pei Dong, Zehua Jin, Gustavo Brunetto, Weibing Chen, Zuan-Tao Lin, Robert Baines, Douglas S. Galvão, Jun Lou, Enrique Barrera, Kaustav Banerjee, Robert Vajtai and Pulickel Ajayan
  Nature Nanotechnology, Vol. 11, No. 5, pp. 465–471, 2016.

2015

• Designing Band-to-Band Tunneling Field-Effect Transistors with 2D Semiconductors for Next Generation Low-Power VLSI
  Wei Cao, Junkai Jiang, Jiahao Kang, Deblina Sarkar, Wei Liu and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), Washington DC, December 7-9, 2015, pp. 12.3.1-12.3.4.

• Electrical Contacts to Two-dimensional Semiconductors
  Adrien Allain, Jiahao Kang, Kaustav Banerjee and Andras Kis
  Nature Materials, Vol. 14, pp. 1195–1205, 2015.
  Read Media Coverage by ECE Department

• Engineered 2D Nanomaterials–Protein Interfaces for Efficient Sensors
  Kiran Kumar Tadi, Tharangattu N. Narayanan, Sivaram Arepalli, Kaustav Banerjee, Sowmya Viswanathan, Dorian Liepmann, Pulickel Ajayan and Venkatesan Renugopalakrishnan
  Journal of Materials Research, Cambridge University Press, Vol. 30, No. 23, pp. 3565-3574, 2015.

• ATLAS-TFET: Toward Green Transistors and Sensors
  Kaustav Banerjee
  International Workshop on Dielectric Thin Films For Future Electron Devices (IWDTF), Miraikan, Tokyo, Japan, November 2-4, pp. 1-4, 2015.
  Invited

• 2D Semiconductor FETs- Projections and Design for Sub-10 nm VLSI
  Wei Cao, Jiahao Kang, Deblina Sarkar, Wei Liu and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Special Issue to commemorate the 60th anniversary of the IEDM, Vol. 62, No. 11, pp. 3459-3469, 2015.

• A Subthermionic Tunnel Field-Effect Transistor with an Atomically Thin Channel
  Deblina Sarkar, Xuejun Xie, Wei Liu, Wei Cao, Jiahao Kang, Yongji Gong, Stephan Kraemer, Pulickel M. Ajayan and Kaustav Banerjee
  Nature, Vol. 526, pp. 91-95, 2015.
  Read Media Coverage by Science Daily, IEEE Spectrum and EE Times

• 2D Crystals for Smart Life
  Kaustav Banerjee
  47th International Conference on Solid State Devices and Materials (SSDM), Sapporo, Japan, Sept. 27-30, 2015.
  Invited Short Course

• 2D Crystals and their Heterostructures for Green Electronics
  Kaustav Banerjee
  Proceedings of the 11th Topical Workshop on Heterostructure Microelectronics, Takayama, Japan, Aug 24-26, pp. 1-10, 2015.
  Invited

• Impact of Contact on the Operation and Performance of Back-Gated Monolayer MoS₂ Field-Effect Transistors
  Wei Liu, Deblina Sarkar, Jiahao Kang, Wei Cao and Kaustav Banerjee
  ACS Nano, Vol. 9, No. 8, pp. 7904–7912, 2015.

• Functionalization of Transition Metal Dichalcogenides with Metallic Nanoparticles: Implications for Doping and Gas-Sensing
  Deblina Sarkar, Xuejun Xie, Jiahao Kang, Haojun Zhang, Wei Liu, Jose Navarrete, Martin Moskovits and Kaustav Banerjee
  Nano Letters, Vol. 15, No. 5, pp. 2852–2862, 2015.

2014

• Performance Evaluation and Design Considerations of 2D Semiconductor based FETs for Sub-10 nm VLSI
  Wei Cao, Jiahao Kang, Deblina Sarkar, Wei Liu and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), San Francisco, Dec. 15-17, 2014, pp. 30.5.1–30.5.4.
  Among 11 Most Significant Papers in IEDM 2014

• Graphene Inductors for High-Frequency Applications – Design, Fabrication, Characterization, and Study of Skin Effect
  Xiang Li*, Jiahao Kang*, Xuejun Xie, Wei Liu, Deblina Sarkar, Junfa Mao and Kaustav Banerjee (*equal contributors)
  IEEE International Electron Devices Meeting (IEDM), San Francisco, Dec. 15-17, 2014, pp. 5.4.1–5.4.4.

• Computational Study of Interfaces between 2D MoS₂ and Surroundings
  Jiahao Kang, Wei Liu and Kaustav Banerjee
  45th IEEE Semiconductor Interface Specialists Conference (SISC), San Diego, CA, December 10-13, 2014.

• A Compact Current–Voltage Model for 2D Semiconductor Based Field-Effect Transistors Considering Interface Traps, Mobility Degradation, and Inefficient Doping Effect
  Wei Cao, Jiahao Kang, Wei Liu and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Vol. 61, No. 12, pp. 4282-4290, 2014.
  SPICE-Compatible Model Available for Download on NanoHub

• 2D Crystal Semiconductors: Intimate Contacts
  Debdeep Jena, Kaustav Banerjee and Grace Huili Xing
  Nature Materials (News & Views), Vol. 13, pp. 1076-1078, Dec. 2014.

• Can 2D-Nanocrystals Extend the Lifetime of Floating-Gate Transistor Based Nonvolatile Memory?
  Wei Cao, Jiahao Kang, Simone Bertolazzi, Andras Kis and Kaustav Banerjee
  IEEE Transactions on Electron Devices, vol. 61, No. 10, pp.3456-3464, 2014.

• Computational Study of Metal Contacts to Monolayer Transition-Metal Dichalcogenide Semiconductors
  Jiahao Kang, Wei Liu, Deblina Sarkar, Debdeep Jena and Kaustav Banerjee
  Physical Review X, Vol. 4, No. 3, pp. 031005, 2014.
  Read Media Coverage by ECE Department

• Low-Frequency Noise in Bilayer MoS₂ Transistor
  Xuejun Xie, Deblina Sarkar, Wei Liu, Jiahao Kang, Ognian Marinov, M. Jamal Deen and Kaustav Banerjee
  ACS Nano, Vol. 8, No. 6, pp. 5633-5640, 2014.

• Subthreshold-Swing Physics of Tunnel Field-Effect Transistors
  Wei Cao, Deblina Sarkar, Yasin Khatami, Jiahao Kang, and Kaustav Banerjee
  AIP Advances, Vol. 4, pp. 067141, 2014.

• Graphene and beyond-graphene 2D crystals for next-generation green electronics
  Jiahao Kang, Wei Cao, Xuejun Xie, Deblina Sarkar, Wei Liu and Kaustav Banerjee
  Proc. SPIE 9083, Micro- and Nanotechnology Sensors, Systems, and Applications VI, 908305, June 5, 2014.
  Invited

• On the Electrostatic-Discharge Robustness of Graphene
  Hong Li, Christian C. Russ, Wei Liu, David Johnsson, Harald Gossner and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Vol. 61, No. 6, pp. 1920-1928, 2014.

• Correction to MoS₂ Field-Effect Transistor for Next-Generation Label-Free Biosensors
  Deblina Sarkar, Wei Liu, Xuejun Xie, Aaron Anselmo, Samir Mitragotri and Kaustav Banerjee
  ACS Nano, 2014.

• MoS₂ Field-Effect Transistor for Next-Generation Label-Free Biosensors
  Deblina Sarkar, Wei Liu, Xuejun Xie, Aaron Anselmo, Samir Mitragotri and Kaustav Banerjee
  ACS Nano, Vol. 8, No. 4, pp. 3992-4003, 2014.
  Read Media Coverage by Phys.org, UCSB Current, UCSB Daily Nexus, Med Device Online, AlChE ChEnected, and Ceramic Tech Today

• Carbon Integrated Electronics
  Hong Li, Yasin Khatami, Deblina Sarkar, Jiahao Kang, Chuan Xu, Wei Liu and Kaustav Banerjee
  in Intelligent Integrated Systems: Technologies, Devices and Architectures. Ed: S. Deleonibus, Pan Stanford Series on Intelligent Nanosystems, pp. 217-274, April 9, 2014.

• High-Performance MoS₂ Transistors with Low-Resistance Molybdenum Contacts
  Jiahao Kang, Wei Liu and Kaustav Banerjee
  Applied Physics Letters, Vol. 104, No. 9, 093106, 2014.
  Among Most Cited Articles in Applied Physics Letters (AIP Highlights)
  Highlighted in APL's New Collection on 2D Transistors, April 27, 2021.

• Controllable and Rapid Synthesis of High-Quality and Large-Area Bernal Stacked Bilayer Graphene using Chemical Vapor Deposition
  Wei Liu, Stephan Krämer, Deblina Sarkar, Hong Li, Pulickel M. Ajayan and Kaustav Banerjee
  ACS Chemistry of Materials, Vol. 26, No. 2, pp 907-915, 2014.
  Read Media Coverage by Phys.org and Science Daily

• On the Electrostatics of Bernal-Stacked Few-Layer Graphene on Surface Passivated Semiconductors
  Yasin Khatami, Hong Li, Wei Liu and Kaustav Banerjee
  IEEE Transactions on Nanotechnology, Vol. 13, No. 1, pp. 94-100, 2014.
  Highlighted on the Cover of IEEE Transactions on Nanotechnology

2013

• High-Performance Few-Layer-MoS₂ Field-Effect-Transistor with Record Low Contact-Resistance
  Wei Liu, Jiahao Kang, Wei Cao, Deblina Sarkar, Yasin Khatami, Debdeep Jena and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), Washington DC, Dec. 9-11, 2013, pp. 499-502.

• Novel Logic Devices based on 2D Crystal Semiconductors: Opportunities and Challenges
  Pei Zhao, Wan-Sik Hwang, Eok Su Kim, Randy Feenstra, Gong Gu, Jiahao Kang, Kaustav Banerjee, Alan Seabaugh, Grace Huili Xing and Debdeep Jena
  IEEE International Electron Devices Meeting (IEDM), Washington DC, Dec. 9-11, 2013, pp. 487-490.
  Invited

• High-Performance Field-Effect-Transistors on Monolayer-WSe₂
  Wei Liu, Wei Cao, Jiahao Kang and Kaustav Banerjee
  ECS Transactions, Vol. 58, No. 7, pp. 281-285, 2013.
  Invited

• 2-Dimensional Tunnel Devices and Circuits on Graphene: Opportunities and Challenges
  Jiahao Kang, Wei Cao, Deblina Sarkar, Yasin Khatami, Wei Liu and Kaustav Banerjee
  3rd Berkeley Symposium on Energy Efficient Electronic Systems, Berkeley, CA, Oct 28-29, 2013, pp. 1-2.

• Prospects of nanoCarbons and Emerging 2D-Crystals for Next-Generation Green Electronics
  Kaustav Banerjee
  Advanced Metallization Conference 2013: 23rd Asian Session, The University of Tokyo, Tokyo, Japan, Oct. 7-10, 2013, pp. 1-2.
  Invited

• Prospects of Graphene Electrodes in Photovoltaics
  Yasin Khatami, Wei Liu, Jiahao Kang and Kaustav Banerjee
  Proc. SPIE 8824, Next Generation (Nano) Photonic and Cell Technologies for Solar Energy Conversion IV, 88240T, September 25, 2013.
  Invited

• 2D Electronics: Graphene and Beyond
  Wei Cao, Jiahao Kang, Wei Liu, Yasin Khatami, Deblina Sarkar and Kaustav Banerjee
  43rd European Solid-State Device Research Conference (ESSDERC), Bucharest, Romania, Sept. 16-20, 2013, pp. 1-8.
  Keynote

• Low-Resistivity Long-Length Horizontal Carbon Nanotube Bundles for Interconnect Applications – Part II: Characterization
  Hong Li, Wei Liu, Alan M. Cassell, Franz Kreupl and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Vol. 60, No. 9, pp. 2870-2876, 2013.

• Low-Resistivity Long-Length Horizontal Carbon Nanotube Bundles for Interconnect Applications – Part I: Process Development
  Hong Li, Wei Liu, Alan M. Cassell, Franz Kreupl and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Vol. 60, No. 9, pp. 2862-2869, 2013.

• Proposal for All-Graphene Monolithic Logic Circuits
  Jiahao Kang, Deblina Sarkar, Yasin Khatami and Kaustav Banerjee
  Applied Physics Letters, Vol. 103, No. 8, 083113, 2013.
  Read Media Coverage by IEEE Spectrum and Extreme Tech

• Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability
  Chuan Xu, Seshadri K. Kolluri, Kazuhiko Endo and Kaustav Banerjee
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 7, pp. 1045-1058, 2013.

• Graphene and Beyond-Graphene 2D-Crystals for Green Electronics
  Kaustav Banerjee, Wei Liu, Jiahao Kang, Yasin Khatami and Deblina Sarkar
  18th Silicon Nanoelectronics Workshop, Kyoto, Japan, June 9-10, 2013, pp. 1-2.
  Invited

• Impact-Ionization Field-Effect-Transistor Based Biosensors for Ultra-Sensitive Detection of Biomolecules
  Deblina Sarkar, Harald Gossner, Walter Hansch and Kaustav Banerjee
  Applied Physics Letters, Vol. 102, No. 20, 203110, 2013.

• VLSI Technology and Circuits
  Kaustav Banerjee and Shuji Ikeda
  in Guide to State-of-the-Art Electron Devices, Ed. J. Burghartz, John Wiley & Sons, Ltd, ISBN: 978-1-1183-4726-3, April 22, 2013.

• Role of Metal Contacts in Designing High-Performance Monolayer n-Type WSe₂ Field-Effect-Transistors
  Wei Liu, Jiahao Kang, Deblina Sarkar, Yasin Khatami, Debdeep Jena and Kaustav Banerjee
  Nano Letters, Vol. 13, no. 5, pp. 1983-1990, 2013.
  Read Media Coverage by Science Daily

• Graphene Nanoribbon Based Negative Resistance Device for Ultra-Low Voltage Digital Logic Applications
  Yasin Khatami, Jiahao Kang and Kaustav Banerjee
  Applied Physics Letters, Vol. 102, No. 4, 043114, 2013.

• Tunnel-Field-Effect-Transistor Based Gas-Sensor: Introducing Gas Detection with a Quantum Mechanical Transducer
  Deblina Sarkar, Harald Gossner, Walter Hansch and Kaustav Banerjee
  Applied Physics Letters, Vol. 102, No. 2, 023110, 2013.

• Physical Modeling of the Capacitance and Capacitive Coupling-Noise of Through-Oxide Vias in FDSOI Based Ultra-High Density 3-D ICs
  Chuan Xu and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Vol. 60, No. 1, pp. 123-131, 2013.

2012

• A Computational Study of Metal-Contacts to Beyond-Graphene 2D Semiconductor Materials
  Jiahao Kang, Deblina Sarkar, Wei Liu, Debdeep Jena and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), pp. 407-410, San Francisco, Dec. 10-12, 2012.

• Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs with Multiple Substrates
  Chuan Xu, Navin Srivastava, Roberto Suaya and Kaustav Banerjee
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, No. 11, pp. 1698-1710, 2012.

• Some Clarifications on “Compact Modeling and Analysis of Through-Si-Via Induced Electrical Noise Coupling in Three-Dimensional ICs
  Chuan Xu, Roberto Suaya and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Vol. 59, No. 10, pp. 2861-2862, 2012.

• ESD Characterization of Atomically-Thin Graphene
  Hong Li, Christian C. Russ, Wei Liu, David Johnsson, Harald Gossner and Kaustav Banerjee
  34th Annual EOS/ESD Symposium, pp. 1-8, Tucson, AZ, September 9-14, 2012.
  Best Paper Award and Best Student Paper Award

• Metal to Multi-Layer Graphene Contact--Part II: Analysis of Contact Resistance
  Yasin Khatami, Hong Li, Chuan Xu and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Vol. 59, No. 9, pp. 2453-2460, 2012.

• Metal to Multi-Layer Graphene Contact--Part I: Contact Resistance Modeling
  Yasin Khatami, Hong Li, Chuan Xu and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Vol. 59, No. 9, pp. 2444-2452, 2012.

• Top Illuminated Inverted Organic UV Photosensors With Single Layer Graphene Electrodes
  Martin Burkhardt, Wei Liu, Christopher G. Shuttle, Kaustav Banerjee and Michael L. Chabinyc
  Applied Physics Letters, Vol. 101, 033302, 2012.

• NEMS based Ultra Energy-Efficient Digital ICs: Materials, Device Architectures, Logic Implementation, and Manufacturability
  Hamed F. Dadgour and Kaustav Banerjee
  Chapter 10 in Microelectronics to Nanoelectronics: Materials, Devices & Manufacturability. Ed: Anupama B. Kaul, CRC Press, ISBN 9781466509542, July 2012.

• Fundamental Limitations of Conventional-FET Biosensors: Quantum-Mechanical-Tunneling to the Rescue
  Deblina Sarkar and Kaustav Banerjee
  Device Research Conference (DRC), pp. 83-84, Penn State University, University Park, PA, June 18-22, 2012.

• Fast Extraction of High-Frequency Parallel Admittance of Through-Silicon-Vias and their Capacitive Coupling-Noise to Active Regions
  Chuan Xu, Roberto Suaya and Kaustav Banerjee
  IEEE International Microwave Symposium, Montréal, Canada, June 17-22, 2012.

• Proposal for Tunnel-Field-Effect-Transistor as Ultra-Sensitive and Label-Free Biosensors
  Deblina Sarkar and Kaustav Banerjee
  Applied Physics Letters, 100, No. 14, 143108, 2012.
  Highlighted in Research Highlights of Nature Nanotechnology

2011

• Graphene Based Green Electronics
  Kaustav Banerjee
  International Workshop on Physics of Semiconductors (IWPSD), IIT-Kanpur, India, Dec 18-22, 2011.
  Invited Talk

• Future of Carbon Nanomaterials as Next-Generation Interconnects and Passives Devices
  Hong Li, Chuan Xu, Deblina Sarkar, Yasin Khatami, Wei Liu and Kaustav Banerjee
  IEEE Electrical Design of Advanced Packaging & Systems (EDAPS) Symposium, Hangzhou, China, Dec 12-14, 2011.

• Some Results Pertaining Electromagnetic Characterization and Model Building for Passive Systems Including TSVs, for 3-D IC’s Applications
  Roberto Suaya, Chuan Xu, Vassilis Kourkoulos, Kaustav Banerjee, Zohaib Mahmood and Luca Daniel
  IEEE Electrical Design of Advanced Packaging & Systems (EDAPS) Symposium, Hangzhou, China, Dec 12-14, 2011.

• Graphene Based Green Electronics
  Kaustav Banerjee
  IEEE Electrical Design of Advanced Packaging & Systems (EDAPS) Symposium, Hangzhou, China, Dec 12-14, 2011.
  Keynote

• Compact Capacitance and Capacitive Coupling-Noise Modeling of Through-Oxide Vias in FDSOI Based Ultra-High Density 3-D ICs
  Chuan Xu and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), pp. 817-820, Washington DC, Dec. 5-7, 2011.

• Synthesis of High-Quality Monolayer and Bilayer Graphene on Copper using Chemical Vapor Deposition
  Wei Liu, Hong Li, Chuan Xu, Yasin Khatami and Kaustav Banerjee
  CARBON, Vol. 49, No. 13, pp. 4122-4130, Nov. 2011.
  Read Media Coverage by Science Daily

• Vertically Stacked and Independently Controlled Twin-Gate MOSFETs on a Single Si-Nanowire
  Xiang Li, Zhixian Chen, Nansheng Shen, Deblina Sarkar, Navab Singh, Kaustav Banerjee, Guo-Qiang Lo and Dim-Lee Kwong
  IEEE Electron Device Letters, Vol. 32, No. 11, pp. 1492-1494, Nov. 2011.

• CMOS Compatible Vertical Silicon Nanowire Gate-All-Around p-type Tunneling FETs with ≤50 mV/decade Subthreshold Swing
  Ramanathan Gandhi, Zhixian Chen, Navab Singh, Kaustav Banerjee and Sungjoo Lee
  IEEE Electron Device Letters, Vol. 32, No. 11, pp. 1504-1506, Nov. 2011.

• Compact Modeling and Analysis of Through-Si-Via Induced Electrical Noise Coupling in 3-D ICs
  Chuan Xu, Roberto Suaya and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Vol. 58, No. 11, pp. 4024-4034, Nov. 2011.
  Incorporated in US Patent

• A Physical Model for Work-Function Variation in Ultra-Short Channel Metal-Gate MOSFETs
  Seid Hadi Rasouli, Chuan Xu, Navab Singh and Kaustav Banerjee
  IEEE Electron Device Letters, Vol. 32, No. 11, pp. 1507-1509, Nov. 2011.

• A Fully Analytical Model for the Series Impedance of Through-Silicon Vias with Consideration of Substrate Effects and Coupling with Horizontal Interconnects
  Chuan Xu, Vassilis Kourkoulos, Roberto Suaya and Kaustav Banerjee
  IEEE Transactions on Electron Devices, vol. 58, no. 10, pp. 3529-3540, Oct. 2011.

• Metallic-Nanoparticle Assisted Enhanced Band-to-Band Tunneling Current
  Deblina Sarkar and Kaustav Banerjee
  Applied Physics Letters, Vol. 99, No. 13, pp. 133116, Sept 26, 2011.

• Carbon Nanotube Vias: Does Ballistic Electron-Phonon Transport Imply Improved Performance and Reliability?
  Hong Li, Navin Srivastava, Jun-Fa Mao, Wen-Yan Yin and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Vol. 58, No. 8, pp. 2689-2701, Aug. 2011.

• Grain-Orientation Induced Quantum Confinement Variation in FinFETs and Multi-Gate Ultra-Thin Body CMOS Devices and Implications for Digital Design
  Seid Hadi Rasouli, Kazuhiko Endo, Jone F. Chen, Navab Singh and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Special Issue on "Characterization of Nano CMOS Variability by Simulation and Measurements," vol. 58, no. 8, pp. 2282-2292, Aug. 2011.

• Demonstration of Vertical Silicon Nanowire Tunnel Field Effect Transistor with Low Subthreshold Slope < 50mV/decade
  Ramanathan Gandhi, Zhixian Chen, Navab Singh, Kaustav Banerjee and Sungjoo Lee
  International Conference on Materials for Advanced Technologies (ICMAT), Singapore, June 26-July 1, 2011.

• Vertical Si-Nanowire n-Type Tunneling FETs With Low Subthreshold Swing (≤ 50 mV/decade) at Room Temperature
  Ramanathan Gandhi, Zhixian Chen, Navab Singh, Kaustav Banerjee and Sungjoo Lee
  IEEE Electron Device Letters, vol. 32, no. 4, pp. 437-439, April 2011.

• Impact of Scaling on the Performance and Reliability Degradation of Metal-Contacts in NEMS Devices
  Hamed F. Dadgour, Muhammad M. Hussain, Alan Cassell, Navab Singh and Kaustav Banerjee
  IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, April 10-14, pp. 280-289, 2011.

• Carbon Based Green Electronics
  Kaustav Banerjee
  ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU 2011), Santa Barbara, CA, March 31-April 1, 2011.
  KEYNOTE

• High-Frequency Behavior of Graphene-Based Interconnects—Part I: Impedance Modeling
  Deblina Sarkar, Chuan Xu, Hong Li, and Kaustav Banerjee
  IEEE Transactions on. Electron Devices, Vol. 58, No. 3, pp. 843-852, March 2011.

• High-Frequency Behavior of Graphene-Based Interconnects—Part II: Impedance Analysis and Implications for Inductor Design
  Deblina Sarkar, Chuan Xu, Hong Li and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Vol. 58, No. 3, pp. 853-859, March 2011.

• Factors Influencing the Synthesis of Monolayer and Bilayer Graphene on Copper using Chemical Vapor Deposition
  Wei Liu, Hong Li, Chuan Xu and Kaustav Banerjee
  38th Conference on the Physics and Chemistry of Surfaces and Interfaces (PCSI-38), San Diego, CA, January 16-20, 2011.

2010

• Electron-hole Duality During Band-to-Band Tunneling Process in Graphene-Nanoribbon Tunnel-FieldEffect Transistors
  Deblina Sarkar, Michael Krall and Kaustav Banerjee
  Applied Physics Letters, Vol. 97, No. 26, p. 263109, Dec 27, 2010.

• A Quantitative Inquisition into ESD Sensitivity to Strain in Nanoscale CMOS Protection Devices
  Deblina Sarkar, Steven Thijs, Dimitri Linten, Christian Russ, Harald Gossner and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 6-8, pp. 808-811, 2010.

• Compact Modeling and Analysis of Coupling Noise Induced by Through-Si-Vias in 3-D ICs
  Chuan Xu, Roberto Suaya and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 6-8, pp. 178-181, 2010.
  Read Media Coverage by Microwaves&RF

• Compact AC Modeling and Performance Analysis of Through-Silicon Vias (TSVs) in 3-D ICs
  Chuan Xu, Hong Li, Roberto Suaya and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Vol. 57, No. 12, pp. 3405-3417, Dec. 2010.

• Carbon-Based Green Electronics
  Kaustav Banerjee
  Materials Research Society (MRS) Fall Symposium, Boston, MA, Nov. 29-Dec. 3, 2010.
  Invited

• Work-function variation induced fluctuation in bias-temperature-instability characteristics of emerging metal-gate devices and implications for digital design
  Seid Hadi Rasouli, Kazuhiko Endo and Kaustav Banerjee
  ACM/IEEE International Conf. on Computer-Aided Design (ICCAD), pp. 714-720, San Jose, CA, Nov. 5-8, 2010.

• Design Optimization of FinFET Domino Logic Considering the Width Quantization Property
  Seid Hadi Rasouli, Hamed F. Dadgour, Kazuhiko Endo, Hanpei Koike, and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Vol. 57, No. 11, pp. 2934-2943, Nov. 2010.

• A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-in Dynamic Gates
  Hamed Dadgour and Kaustav Banerjee
  IEEE Transactions on VLSI Systems, Vol. 18, No. 11, pp. 1567-1577, Nov. 2010.

• A Novel Enhanced Electric-Field Impact-Ionization MOS Transistor
  Deblina Sarkar, Navab Singh and Kaustav Banerjee
  IEEE Electron Device Letters, Vol. 31, No. 11, pp. 1175-1177, Nov. 2010.

• A Thermal Simulation Process Based on Electrical. Modeling for Complex Interconnect, Packaging and 3DI Structures
  Lijun Jiang, Chuan Xu, Barry J. Rubin, Alan J. Weger, Alina Deutsch, Howard Smith, Alain Caron and Kaustav Banerjee
  IEEE Trans. Advanced Packaging, Vol. 33, No. 4, pp. 777-786, Nov. 2010.

• Grain-Orientation Induced Work-Function Variation in Nanoscale Metal-Gate Transistors––Part I: Modeling, Analysis, and Experimental Validation
  Hamed F. Dadgour, Kazuhiko Endo, Vivek De and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Vol. 57, No. 10, pp. 2504-2514, 2010.

• Grain-Orientation Induced Work-Function Variation in Nanoscale Metal-Gate Transistors––Part II: Implications for Process, Device, and Circuit Design
  Hamed F. Dadgour, Kazuhiko Endo, Vivek De and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Vol. 57, No. 10, pp. 2515-2525, 2010.

• A New Paradigm in the Design of Energy-Efficient Digital Circuits Using Laterally-Actuated Double-Gate NEMS
  Hamed F. Dadgour, Muhammad M. Hussain and Kaustav Banerjee
  IEEE International Symposium on Low Power Electronics and Design (ISLPED), Austin, TX, August 18-20, pp. 7-12, 2010.

• Prospects of Carbon Nanomaterials for Next-Generation Green Electronics
  Kaustav Banerjee, Hong Li, Chuan Xu, Yasin Khatami, Hamed F. Dadgour, Deblina Sarkar and Wei Liu
  IEEE NANO, Kintex, Seoul, August 17-20, pp. 1-6, 2010.

• Carbon Nanomaterials: The Ideal Interconnect Technology for Next-Generation ICs
  Hong Li, Chuan Xu and Kaustav Banerjee
  IEEE Design and Test of Computers, Special Issue on Emerging Interconnect Technologies for Gigascale Integration, pp. 20-31, July/August, 2010.
  Invited

• Accurate Calculations of the High-frequency Impedance Matrix for VLSI Interconnects and Inductors above a Multi-layer Substrate: A VARPRO success story
  Navin Srivastava, Roberto Suaya, V. Pereyra and Kaustav Banerjee
  in Exponential Data Fitting and its Applications, Editors: V. Pereyra and G. Scherer. Bentham Science Publishers, ISBN: 978-1-60805-048-2, 2010.

• Effect of Grain Orientation on NBTI Variation and Recovery in Emerging Metal-Gate Devices
  Seid Hadi Rasouli and Kaustav Banerjee
  IEEE Electron Device Letters, Vol. 31, No. 8, pp. 794-796, Aug 2010.

• Compact AC Modeling and Performance Analysis of Through-Silicon Vias (TSVs) in 3-D ICs
  Chuan Xu, Hong Li, Roberto Suaya and Kaustav Banerjee
  28th Progress In Electromagnetics Research Symposium (PIERS), Cambridge, MA, pp.1-2, 2010.

• Graphene Based Heterostructure Tunnel-FETs for Low-Voltage/High-Performance ICs
  Yasin Khatami, Michael Krall, Hong Li, Chuan Xu and Kaustav Banerjee
  in Proceedings 68th Device Research Conference (DRC), Notre Dame, IN, June 21-23, 2010, pp. 65-66.

• CAD for Nanoelectronics: Earlier the Better
  Kaustav Banerjee
  IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH’08), June 17-18, 2010, Anaheim, CA PANEL: CAD for Nanoelectronic Circuits and Architectures – Are we there yet?

• Design and Analysis of Compact Ultra Energy-Efficient Logic Gates Using Laterally-Actuated DoubleElectrode NEMS
  Hamed F. Dadgour, Muhammad M. Hussain, Casey Smith and Kaustav Banerjee
  Design Automation Conference (DAC), Anaheim, CA, June 13-18, 2010, pp. 893-896.

• AC Conductance Modeling and Analysis of Graphene Nanoribbon Interconnects
  Deblina Sarkar, Chuan Xu, Hong Li and Kaustav Banerjee
  in Proceedings 13th IEEE International Interconnect Technology Conference (IITC), San Francisco, CA, June 7- 9, pp.1-3, 2010.

• An Efficient 3D Green’s Function Approach for Fast Impedance Extraction of Interconnects and Spiral Inductors in CMOS RF/Millimeter-wavelength Circuits
  Navin Srivastava, Roberto Suaya and Kaustav Banerjee
  IEEE International Interconnect Technology Conference (IITC), San Francisco, CA, June 7-9, pp. 1-3, 2010.

• A Built-in Aging Detection and Compensation Technique for Improving Reliability of Nanoscale CMOS Designs
  Hamed F. Dadgour and Kaustav Banerjee
  IEEE International Reliability Physics Symposium (IRPS), May 2-6, Anaheim, CA, pp. 822-825, 2010.

• Corrections to “Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate”
  Navin Srivastava, Chuan. Xu, Roberto Suaya and Kaustav Banerjee
  IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 29, No. 5, pp. 849-849, May 2010.

• Carbon based Nanomaterials as Interconnects and Passives for Next-Generation VLSI and 3-D ICs
  Kaustav Banerjee
  IEEE Workshop on Microelectronics and Electron Devices (WMED), Boise, Idaho, April 16, 2010.
  Invited Tutorial

• Carbon Based Active and Passive Devices for Next-Generation ICs
  Kaustav Banerjee, Wei Liu, Hong Li, Yasin Khatami and Chuan Xu
  Ultimate Integration in Silicon (ULIS), Glasgow, Scotland, March 17-19, 2010.
  Invited Plenary Talk

• Aging-Resilient Design of Pipelined Architectures using Novel Detection and Correction Circuits
  Hamed Dadgour and Kaustav Banerjee
  Design and Test in Europe (DATE), Dresden, Germany March 8-12, pp. 244-249, 2010.

• Efficient 3D High-frequency Impedance Extraction for General Interconnects and Inductors Above a Layered Substrate
  Navin Srivastava, Roberto Suaya and Kaustav Banerjee
  Design and Test in Europe (DATE), Dresden, Germany March 8-12, pp. 459-464, 2010.

2009

• Single wall carbon nanotube-Aptamer Based Biosensors
  S. H. Varghese, Y. Nakajima, Y. Yoshida, T. Maekawa, T. Hanajiri, Kaustav Banerjee and D. S. Kumar
  7th International Symposium on Bioscience and Nanotechnology, Tokyo, Japan, December 20-21, 2009.

• Carbon Nanomaterial based Interconnects and Passives for Next-Generation ICs
  Kaustav Banerjee, Hong Li and Chuan Xu
  XVth International Workshop on Physics of Semiconductor Devices (IWPSD), New Delhi India, Dec. 15-19, 2009.
  Invited

• Impact of Strain Engineering and Channel Orientation on the ESD Performance of Nanometer Scale CMOS Devices
  Jing Lu, Charvaka Duvvury, Harald Gossner and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), Baltimore, Dec. 6-9, 2009.

• Compact AC Modeling and Analysis of Cu, W, and CNT based Through-Silicon Vias (TSVs) in 3-D ICs
  Chuan Xu, Hong Li, Roberto Suaya and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), Baltimore, Dec. 6-9, 2009. 

• Green Electronics using Graphene based Nanomaterials
  Kaustav Banerjee
  Emerging Technologies in Solid State Devices Workshop, Baltimore, MD, December 5 - 6, 2009.

• Experimental Investigation of ESD Performance for Strained Silicon Nano-Devices
  Deblina Sarkar, Harald Gossner and Kaustav Banerjee
  ESD Forum, Berlin, Dec. 1-2, 2009.

• Variability Analysis of FinFET-Based Devices and Circuits Considering Electrical Confinement and Width Quantization
  Seid Hadi Rasouli, Kazuhiko Endo and Kaustav Banerjee
  International Conf. on Computer-Aided Design (ICCAD), San Jose, Nov. 2-5, pp. 505-512, 2009.

• Fast 3-D Thermal Analysis of Complex Interconnect Structures Using Electrical Modeling and Simulation Methodologies
  Chuan Xu, Lijun Jiang, Seshadri K. Kolluri, Barry J. Rubin, Alina Deutsch, Howard Smith and Kaustav Banerjee
  International Conf. on Computer-Aided Design (ICCAD), San Jose, Nov. 2-5, pp. 658-665, 2009.

• Steep Subthreshold Slope n- and p-type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits
  Yasin Khatami and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Vol. 56, No. 11, pp. 2752-2761, Nov. 2009.

• Hybrid NEMS-CMOS Integrated Circuits: A Novel Strategy for Energy-Efficient Designs
  Hamed Dadgour and Kaustav Banerjee
  IET Transactions on Computers and Digital Techniques—Special Issue on Advances in Nanoelectronics Circuits and Systems, Vol. 3, No. 6, pp. 593-608, Nov. 2009.

• Carbon Based Active and Passive Devices for Next-Generation ICs
  Kaustav Banerjee, Hamed Dadgour, Yasin Khatami, Hong Li and Chuan Xu
  Global COE International Symposium on Silicon Nano Devices in 2030: Prospects by World’s Leading Scientists, Oct. 13-14, Tokyo, 2009.
• Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status and Prospects
  Kaustav Banerjee, Hong Li and Chuan Xu
  International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, Oct. 7-9, 2009.

• High-Frequency Analysis of Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design
  Hong Li and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Vol. 56, No. 10, pp. 2202-2214, Oct 2009.

• Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status and Prospects
  Hong Li, Chuan Xu, Navin Srivastava and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Special Issue on Compact Interconnect Models for Gigascale Integration, Vol. 56, No. 9, pp. 1799-1821, Sep 2009.
  Invited and Highlighted on the Journal Cover

• Prospects of Carbon Nanomaterials in VLSI for Interconnections and Energy Storage
  Kaustav Banerjee, Hong Li and Chuan Xu
  31st Annual EOS/ESD Symposium, Anaheim, CA, Aug 30-Sept 4, 2009.
  Invited

• Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status and Prospects
  Kaustav Banerjee, Hong Li, Navin Srivastava and Chuan Xu
  Progress in Electromagnetics Research Symposium (PIERS), Moscow, Russia, August 18-21, 2009.

• An Analytical Treatment of High-frequency Impedance Extraction for Interconnects and Inductors in the Presence of a Multi-layer Substrate
  Roberto Suaya, Navin Srivastava and Kaustav Banerjee
  Progress in Electromagnetics Research Symposium (PIERS), Moscow, Russia, August 18-21, 2009.

• Modeling, Analysis and Design of Graphene Nano-Ribbon Interconnects
  Chuan Xu, Hong Li and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Vol. 56, No. 8, pp. 1567-1578, Aug 2009.

• Graphene Based Nanomaterials for VLSI Interconnect and Energy-Storage Applications
  Kaustav Banerjee
  ACM/IEEE System Level Interconnect Prediction (SLIP), San Francisco, CA, July 26, 2009.
  Invited Tutorial

• On the Applicability of Single-Walled Carbon Nanotubes as VLSI Interconnections
  Navin Srivastava, Hong Li, Franz Kreupl and Kaustav Banerjee
  IEEE Transactions on Nanotechnology, Vol. 8, No. 4, pp. 542-559, July 2009.

• Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multi-layer Conductive Substrate
  Navin Srivastava, Roberto Suaya and Kaustav Banerjee
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, No. 7, pp. 1047-1060, July 2009.
  This work is core technology in CALIBRE xL / xACT (extraction tools) from Mentor Graphics

• Scaling Analysis of Graphene Nanoribbon Tunnel-FETs
  Yasin Khatami and Kaustav Banerjee
  Device Research Conference (DRC), pp. 217-218, Penn State University, University Park, PA, June 22-24, pp. 217-218, 2009.

• Carbon Nanomaterials for Next Generation Interconnects and Passives: Physics, Status and Prospects
  Kaustav Banerjee
  International Electrostatic Discharge Workshop (IEW), Lake Tahoe, CA, May 18-21, 2009.
  Keynote

• Graphene Based Transistors: Physics, Status and Future Perspectives
  Kaustav Banerjee, Yasin Khatami, Chaitanya Kshirsagar and S. Hadi Rasouli
  International Symposium on Physical Design (ISPD), San Diego, CA, March 29-April 1, 2009.

• Carbon Nanomaterials for Next Generation Interconnects and Passives: Physics, Status and Prospects
  Kaustav Banerjee
  18th Materials for Advanced Metallization Conference (MAM), Grenoble, France, March 8-11.

• CMOS vs. Nano: Comrades or Rivals?
  Kaustav Banerjee
  17th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, CA, Feb 22-24Panel: CMOS vs. Nano: Comrades or Rivals?
  Invited Panel

• High-Speed Low-Power FinFET Based Domino Logic
  Seid Hadi Rasouli, Hanpei Koike and Kaustav Banerjee
  14th Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, Jan. 19-22, 2009.

2008

• Graphene Nano-Ribbon (GNR) Interconnects: A Genuine Contender or a Delusive Dream?
  Chuan Xu, Hong Li and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), pp. 201-204, San Francisco, Dec. 15-17, 2008.

• High-Frequency Effects in Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design
  Hong Li and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), pp. 525-528, San Francisco, Dec. 15-17, 2008.

• Scaling and Variability Analysis of CNT-Based NEMS Devices and Circuits with Implications for Process Design
  Hamed Dadgour, Alan M. Cassell and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), pp. 529-532, San Francisco, Dec. 15-17, 2008.

• Modeling and Analysis of Grain-Orientation Effects in Emerging Metal-Gate Devices and Implications for SRAM Reliability
  Hamed Dadgour, Kazuhiko Endo, Vivek De and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), pp. 705-708, San Francisco, Dec. 15-17, 2008.

• Accurate Intrinsic Gate Capacitance Model for Carbon Nanotube-Array Based FETs Considering Screening Effect
  Chaitanya Kshirsagar, Hong Li, Tomas E. Kopley and Kaustav Banerjee
  IEEE Electron Device Letters, Vol. 29, No. 12, pp. 1408-1411, Dec. 2008.

• Statistical Modeling of Metal-Gate Work-Function Variability in Emerging Device Technologies and Implications for Circuit Design
  Hamed Dadgour, Vivek De and Kaustav Banerjee
  IEEE International Conference on Computer-Aided Design (ICCAD), pp. 270-277, San Jose, Nov. 10-13, 2008.
  Nominated for the IEEE/ACM William J. McCalla Best Paper Award

• A Design-Specific and Thermally-Aware Methodology for Trading-off Power and Performance in Leakage-Dominant CMOS Technologies
  Sheng-Chih Lin and Kaustav Banerjee
  IEEE Transactions on Very Large Scale Integration Systems, Vol. 16, No. 11, pp. 1488-1498, Nov. 2008.

• Current Status and Future Perspectives of Carbon Nanotube Interconnects
  Kaustav Banerjee, Hong Li and Navin Srivastava
  IEEE EMC Symposium, Detroit, MI, August 18-22, 2008.
  Invited

• Current Status and Future Perspectives of Carbon Nanotube Interconnects
  Kaustav Banerjee, Hong Li and Navin Srivastava
  IEEE NANO: 8th International Conference on Nanotechnology, pp. 432-436, Arlington, TX, August 18-21, 2008.

• Carbon Nanotube Interconnects for Next Generation ICs
  Kaustav Banerjee
  Summer School on Nanoelectronic Circuits and Tools, EPFL, Lausanne, Switzerland, July 14-18, 2008.
  Invited

• Hybrid NEMS-CMOS Circuits
  Kaustav Banerjee
  IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH’08), June 12-13, 2008, Anaheim, CA Panel: Non-CMOS NanoElectronics – Will it ever be real?
  Invited Panel

• Analysis and Implications of Parasitic and Screening Effects on the High-Frequency/RF Performance of Tunneling-Carbon Nanotube FETs
  Chaitanya Kshirsagar, Mohamed N. El-Zeftawi and Kaustav Banerjee
  IEEE/ACM Design Automation Conference (DAC), Anaheim, CA, June 8-13, pp. 250-255, 2008.

• Circuit Modeling and Performance Analysis of Multi-Walled Carbon Nanotube Interconnects
  Hong Li, Wen-Yan Yin, Kaustav Banerjee and Jun-Fa Mao
  IEEE Transactions on Electron Devices, Vol. 55, No. 6, pp. 1328-1337, 2008.

• High-Frequency Effects in Carbon Nanotube Interconnects
  Kaustav Banerjee
  12th IEEE Workshop on Signal Propagation on Interconnects (SPI), Avignon, Pope's Palace, France, May 12- 15, 2008.
  Keynote

• 3D Device Modeling of Damage Due to Filamentation Under an ESD Event in Nanometer Scale Drain Extended NMOS (DE-NMOS)
  Amitabh Chatterjee, Sameer Pendharkar, Haral Gossner, Charvaka Duvvury and Kaustav Banerjee
  IEEE International Reliability Physics Symposium (IRPS), pp. 639-640, Phoenix, AZ, April 27-May 1, 2008.

• High-Frequency Mutual Impedance Extraction of VLSI Interconnects in the Presence of a Multi-layer Conducting Substrate
  Navin Srivastava, Roberto Suaya and Kaustav Banerjee
  IEEE Design and Test in Europe (DATE), pp.42-431, Munich, Germany, March 10-14, 2008.

• Thermal Challenges of 3-D ICs
  Sheng-Chih Lin and Kaustav Banerjee
  in Wafer Level 3-D ICs Process Technology, Editors: Chuan Seng Tan, Ronald J. Gutmann, L. Rafael Reif, Springer, ISBN: 978-0-387-76532-7, 2008.

• Cool Chips: Opportunities and Implications for Power and Thermal Management
  Sheng-Chih Lin and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Special Issue on Device Technologies and Circuit Techniques for Power Management, Vol. 55, No. 1, pp. 245-255, 2008.
  Highlighted on the Journal Cover

2007

• Power and Thermal Management in the Nanometer Era
  Kaustav Banerjee
  IEEE CPMT EDAPS, Taipei, Taiwan, December 15-17, 2007.

• A Fast Semi-numerical Technique for the Solution of the Poisson-Boltzmann Equation in a Cylindrical Nanowire
  Ashok T. Ramu, Manjeri P. Anantram and Kaustav Banerjee
  IEEE International Semiconductor Device Research Symposium (ISDRS), pp. 1-2, College Park, MD, December 12-14, 2007.

• Modeling and Analysis of Intrinsic Gate Capacitance for Carbon Nanotube Array Based Devices Considering Variation in Screening Effect and Diameter
  Chaitanya Kshirsagar and Kaustav Banerjee
  IEEE International Semiconductor Device Research Symposium (ISDRS), pp. 1-2, College Park, MD, December 12-14, 2007.

• Performance Analysis of Multi-Walled Carbon Nanotube Based Interconnects
  Hong Li, Wen-Yan Yin, Jun-Fa Mao and Kaustav Banerjee
  IEEE International Semiconductor Device Research Symposium (ISDRS), pp. 1-2, College Park, MD, December 12-14, 2007.

• A Microscopic Understanding of Nanometer Scale DENMOS Failure Mechanism Under ESD Conditions
  Amitabh Chatterjee, Sameer Pendharkar, Yen-Yi Lin, Charvaka Duvvury and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), pp. 181-184, Washington DC, Dec. 10-12, 2007.

• Modeling and Analysis of Self-Heating in FinFET Devices for Improved Circuit and EOS/ESD Performance
  Seshadri Kolluri, Kazuhiko Endo, Eiichi Suzuki and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), pp. 177-180, Washington DC, Dec. 10-12, 2007.

• Carbon Nanotube Vias: A Reality Check
  Hong Li, Navin Srivastava, Jun-Fa Mao, Wen-Yan Yin and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), pp. 207-210, Washington DC, Dec. 10-12, 2007.

• A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part I: Electrothermal Couplings and Full-Chip Package Thermal Model
  Sheng-Chih Lin, Greg Chrysler, Ravi Mahajan, Vivek De and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Vol. 54, No. 12, pp. 3342-3350, 2007.

• A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part II: Implementation and Implications for Power Estimation and Thermal Management
  Sheng-Chih Lin, Greg Chrysler, Ravi Mahajan, Vivek De and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Vol. 54, No. 12, pp. 3351-3360, 2007.

• A Statistical Framework for Estimation of Full-Chip Leakage-Power Distribution under Parameter Variations
  Hamed Dadgour, Sheng-Chih Lin and Kaustav Banerjee
  IEEE Transactions on Electron Devices, Vol. 54, No. 11, pp. 2930-2945, Nov. 2007.

• Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications
  Hamed F. Dadgour and Kaustav Banerjee
  IEEE/ACM Design Automation Conference (DAC), pp. 306-311, San Diego, CA, June 4-8, 2007.

• Nano-enhanced Architectures: Using Carbon Nanotube Interconnects in Cache Design
  Banit Agrawal, Navin Srivastava, Frederic T. Chong, Kaustav Banerjee and Timothy Sherwood
  4th Workshop on Non-Silicon Computing (NSC-4) held in conjunction with the International Symposium on Computer Architecture (ISCA'07 workshop), San Diego, California, June 2007.

• An Insight into the High Current ESD Behavior of Drain Extended NMOS (DENMOS) Devices in Nanometer Scale CMOS Technologies
  Amitabh Chatterjee, Sameer Pendharkar, Yen-Yi Lin, Charvaka Duvvury and Kaustav Banerjee
  IEEE International Reliability Physics Symposium (IRPS), pp. 608-609, Phoenix, AZ, April 15-19, 2007.

• Electrothermal Engineering in the Nanometer Era
  Kaustav Banerjee
  17th ACM Great Lakes Symposium on VLSI (GLSVLSI), Stresa-Lago Maggiore, Italy, March 11-13, 2007.
  Invited Tutorial

• SoC Communication Architectures: Technology, Current Practice, Research and Trends
  Kaustav Banerjee, Luca Benini, Nikil Dutt, Kanishka Lahiri and Sudeep Pasricha
  VLSI Design Conference, Bangalore, India, Jan. 6-10, 2007.
  Invited Tutorial

• 3D-Integration for Introspection
  Shashidhar Mysore, Banit Agrawal, Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee and Timothy Sherwood
  IEEE Micro: Micro's Top Picks from Computer Architecture Conferences (IEEE Micro - top pick), pp. 77-83, January-February 2007.

2006

• Can Carbon Nanotubes Extend the Lifetime of On-Chip VLSI Interconnections?
  Kaustav Banerjee
  IEEE-CPMT Electrical Design of Advanced Packaging Systems (EDAPS), Shanghai, China, December 17-19, 2006.

• An Electrothermally-Aware Full-Chip Substrate Temperature Gradient Evaluation Methodology for Leakage Dominant Technologies with Implications for Power Estimation and Hot-Spot Management
  Sheng-Chih Lin and Kaustav Banerjee
  IEEE International Conference on Computer-Aided Design (ICCAD), pp. 568-574, San Jose, CA, Nov. 5-9, 2006.

• Power and Thermal Challenges for 65 nm and Below
  Kaustav Banerjee, Paul Coteus and Vivek De
  IEEE International Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 5-9, 2006.
  Invited Tutorial

• What are Carbon Nanotubes?
  Kaustav Banerjee
  ACM SIGDA Newsletter, Vol. 36, No. 21, Nov. 2006.

• Introspective 3-D Chips
  Shashidhar C. Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee and Tim Sherwood
  International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pp. 264-273, San Jose, CA, Oct. 25-25, 2006.
  IEEE MICRO Top Pick

• Carbon Nanotubes: An Emerging Alternative for On-Chip VLSI Interconnects
  Kaustav Banerjee
  Future Directions in IC and Package Design Workshop (FDIP), Scottsdale, AZ, Oct. 22, 2006.

• Prospects for Carbon Nanotube Interconnects
  Kaustav Banerjee
  23rd Advanced Metallization Conference (AMC), San Diego, CA, Oct. 16-19, 2006.

• Modeling and Extraction of Nanometer Scale Interconnects: Challenges and Opportunities
  Roberto Suaya, Rafael Escovar, Salvador Ortiz, Kaustav Banerjee and Navin Srivastava
  23rd Advanced Metallization Conference, San Diego, CA, Oct. 16-19, 2006.

• Thermal Dissipation in Multilayer Devices
  Rajiv V. Joshi, Kaustav Banerjee, T. Smy, K. Guarini, C.T. Chuang and N. Zamadmar
  23rd Advanced Metallization Conference, San Diego, CA, Oct. 16-19, 2006.

• Can Carbon Nanotubes Extend the Lifetime of On-Chip Electrical Interconnections?
  Kaustav Banerjee, Sungjun Im and Navin Srivastava
  IEEE Conference on Nano Networks (Nano-Net), Lausanne, Switzerland, Sept. 14-16, 2006.

• A Thermally-Aware Performance Analysis of Vertically Integrated (3-D) Processor-Memory Hierarchy
  Gian L. Loi, Banit Agarwal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood and Kaustav Banerjee
  ACM Design Automation Conference (DAC), pp. 991-996, San Francisco, CA, July 24-28, 2006.

• A Novel Variation-Aware Low-Power Keeper Architecture for Wide Fan-in Dynamic Gates
  Hamed F. Dadgour, Rajiv V. Joshi and Kaustav Banerjee
  ACM Design Automation Conference (DAC), pp. 977-982, San Francisco, CA, July 24-28, 2006.

• Are Carbon Nanotubes the Future of VLSI Interconnections?
  Kaustav Banerjee and Navin Srivastava
  ACM Design Automation Conference (DAC), pp. 809-814, San Francisco, CA, July 24-28, 2006.

• Emerging Interconnect Technologies based on Carbon Nanotubes
  Navin Srivastava and Kaustav Banerjee
  IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 27-29, 2006.
  Invited Tutorial

• Electrothermal Engineering in the Nanometer Era: From Devices and Interconnects to Circuits and Systems
  Kaustav Banerjee, Sheng-Chih Lin and Navin Srivastava
  Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 223-230, Yokohama, Japan, Jan. 24-27, 2006.

2005

• New Physical Insight and Modeling of Second Breakdown (It₂) Phenomenon in Advanced ESD Protection Devices
  Amitabh Chatterjee, Charvaka Duvvury and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), pp. 203-206, Washington DC, Dec. 5-7, 2005.

• Carbon Nanotube Interconnects: Implications for Performance, Power Dissipation and Thermal Management
  Navin Srivastava, Rajiv V. Joshi and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), pp. 257-260, Washington DC, Dec. 5-7, 2005.

• Analysis and Implications of IC Cooling for Deep Nanometer Scale CMOS Technologies
  Sheng-Chih Lin, Ravi Mahajan, Vivek De and Kaustav Banerjee
  IEEE International Electron Devices Meeting (IEDM), pp. 1041-1044, Washington DC, Dec. 5-7, 2005.
  Highlighted Paper of IEDM 2005

• Scaling Analysis of Multilevel Interconnect Temperatures in High Performance ICs
  Sungjun Im, Navin Srivastava, Kaustav Banerjee and Kenneth E. Goodson
  IEEE Transactions on Electron Devices, Vol. 52, No. 12, pp. 2710-2719, 2005.

• Performance Analysis of Carbon Nanotube Interconnects for VLSI Applications
  Navin Srivastava and Kaustav Banerjee
  IEEE International Conference on Computer-Aided Design (ICCAD), pp. 383-390, San Jose, CA, November 6-10, 2005.
  2015 ICCAD Ten Year Retrospective Most Influential Paper Award

• Thermal Scaling Analysis of Multilevel Cu/Low-k Interconnect Structures in Deep Nanometer Scale Technologies
  Sungjun Im, Navin Srivastava, Kaustav Banerjee and Kenneth E. Goodson
  Proceedings of the 22nd International VLSI Multilevel Interconnect Conference (VMIC), pp. 525-530, Fremont, CA, October 3-6, 2005.
  Outstanding Student Paper Award

• A Thermally Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs
  Sheng-Chih Lin, Navin Srivastava and Kaustav Banerjee
  IEEE International Conference on Computer Design (ICCD), pp. 411-416, San Jose, October 2-5, 2005.

• Thermal Modeling of Bonded SOI/3D ICs
  Rajiv V. Joshi, Kaustav Banerjee, T. Smy, K. Guarini, C. T. Chuang, A. Devgan and N. Zamadmar
  Advanced Metallization Conference (AMC), pp. 25-31, Colorado Springs, CO. Sept. 26-29, 2005.

• Interconnect Modeling and Analysis in the Nanometer Era: Cu and Beyond
  Kaustav Banerjee, Sungjun Im and Navin Srivastava
  Advanced Metallization Conference (AMC), Colorado Springs, CO. Sept. 26-29, 2005.

• Supply and Power Optimization in Leakage Dominant Technologies
  Man Lung Mui, Kaustav Banerjee and Amit Mehrotra
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 9, pp. 1362-1371, 2005.

• A Probabilistic Framework for Power-Optimal Repeater Insertion for Global Interconnects Under Parameter Variations
  Vineet Wason and Kaustav Banerjee
  International Symposium on Low Power Electronic Design (ISLPED), pp. 131-136, San Diego, CA, August 8-10, 2005.
  Nominated for the Best Paper Award

• Modeling and Analysis of Non-Uniform Substrate Temperature Effects on Global ULSI Interconnects
  Amir H. Ajami, Kaustav Banerjee and Massoud Pedram
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 6, pp. 849-861, 2005.

• Mechanisms Leading to Erratic Snapback Behavior in Bipolar Junction Transistors with Base Emitter Shorted
  Amitabh Chatterjee, Ronald D. Schrimpf, Sameer Pendharkar and Kaustav Banerjee
  Journal of Applied Physics, Vol. 97, 084504, April 15, 2005.

• Impact of On-Chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits
  Navin Srivastava, Xiaoning Qi and Kaustav Banerjee
  IEEE International Symposium on Quality Electronic Design, pp. 346-351, San Jose, CA, March 21-23, (ISQED), 2005.

• Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI
  Amir H. Ajami, Kaustav Banerjee and Massoud Pedram
  International Journal of Analog Integrated Circuits and Signal Processing, Vol. 42, No. 3, pp. 277-290, Springer, 2005.

• Emerging Nanoelectronics: Life With and After CMOS, Vol. 1
  Adrian M. Ionescu and Kaustav Banerjee
  Springer (Kluwer), ISBN: 1-4020-7533-2, 622 pp. (2005)

• Emerging Nanoelectronics: Life With and After CMOS, Vol. 2
  Adrian M. Ionescu and Kaustav Banerjee
  Springer (Kluwer), ISBN: 1-4020-7915-X, 340 pp. (2005)

• Emerging Nanoelectronics: Life With and After CMOS, Vol. 3
  Adrian M. Ionescu and Kaustav Banerjee
  Springer (Kluwer), ISBN: 1-4020-7916-8, 428 pp. (2005)

2004

• Analytical Modelling of Single Electron Transistor (SET) for Hybrid CMOS-SET Analog IC Design
  Santanu Mahapatra, Vaibhav Vaish, Christoph Wasshuber, Kaustav Banerjee and Adrian Ionescu
  IEEE Transactions on Electron Devices, Vol. 51, No. 11, pp. 1772-1782, Nov. 2004.

• Leakage and Variation Aware Thermal Management of Nanometer Scale ICs
  Kaustav Banerjee, Sheng-Chih Lin and Vineet Wason
  Proceedings of the IMAPS-Advanced Technology Workshop on Thermal Management, Oct. 25-27, Palo Alto, CA, 2004.

• Interconnect Challenges for Nanoscale Electronic Circuits
  Navin Srivastava and Kaustav Banerjee
  TMS Journal of Materials (JOM), Special Issue on Nanoelectronics, Vol. 56, No. 10, pp. 30-31, October 2004.
  Invited

• Nanometer Scale Interconnect Challenges
  Kaustav Banerjee
  State-Of-The-Art Seminar, 21st International VLSI Multilevel Interconnection Conference (VMIC), Hawaii, Sept. 29-Oct. 2, 2004.

• A Comparative Scaling Analysis of Metallic and Carbon Nanotube Interconnections for Nanometer Scale VLSI Technologies
  Navin Srivastava and Kaustav Banerjee
  Proceedings of the 21st International VLSI Multilevel Interconnect Conference (VMIC), pp. 393-398, Hawaii, Sept. 29-Oct. 2, 2004.

• A Probabilistic Framework to Estimate Full-Chip Subthreshold Leakage Power Distribution Considering Within-Die and Die-to-Die P-T-V Variations
  Songqing Zhang, Vineet Wason and Kaustav Banerjee
  International Symposium on Low Power Electronic Design (ISLPED), pp. 156-161, Newport Beach, CA, August 9-11, 2004.

• Simultaneous Optimization of Supply and Threshold Voltages for Low-Power and High-Performance Circuits in the Leakage Dominant Era
  Anirban Basu, Sheng-Chih Lin, Vineet Wason, Amit Mehrotra and Kaustav Banerjee
  ACM Design Automation Conference (DAC), pp. 884-887, San Diego, CA, June 7-10, 2004.

• Modeling Techniques and Verification Methodologies for Substrate Coupling Effects in Mixed-Signal System-on-Chip Designs
  Adil Koukab, Kaustav Banerjee and Michel Declercq
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 6, pp. 823-836, 2004.

• Impact of Off-state Leakage Current on Electromigration Design Rules for Nanometer Scale CMOS Technologies
  Sheng-Chih Lin, Anirban Basu, Ali Keshavarzi, Vivek De and Kaustav Banerjee
  IEEE Annual International Reliability Physics Symposium (IRPS), pp. 74-78, Phoenix, AZ, April 25-29, 2004.

• A Comprehensive Analytical Capacitance Model of a Two Dimensional Nanodot Array
  Anirban Basu, Sheng-Chih Lin, Christoph Wasshuber, Adrian Ionescu and Kaustav Banerjee
  IEEE International Symposium on Quality Electronic Design (ISQED), pp. 259-264, San Jose, CA, March 22-24, 2004.

• Power Supply Optimization in Sub-130 nm Leakage Dominant Technologies
  Man L Mui, Kaustav Banerjee and Amit Mehrotra
  IEEE International Symposium on Quality Electronic Design (ISQED), pp. 409-414, San Jose, CA, March 22-24, 2004.

• A Global Interconnect Optimization Scheme for Nanometer Scale VLSI with Implications for Latency, Bandwidth and Power Dissipation
  Man Lung Mui, Kaustav Banerjee and Amit Mehrotra
  IEEE Transactions on Electron Devices, Vol. 51, No. 2, pp. 195-203, February 2004.

2003

• 3D ICs DSM Interconnect Performance Modeling and Analysis
  Shukri J. Souri, T-Y. Chiang, Pawan Kapur, Kaustav Banerjee and Krishna C. Saraswat
  in Interconnect Technology and Design for Gigascale Integration, Editors: Jeffrey A. Davis and James D. Meindl, Springer, ISBN: 1-4020-7606-1, 2003.

• A Self-Consistent Junction Temperature Estimation Methodology for Nanometer Scale ICs with Implications for Performance and Thermal Management
  Kaustav Banerjee, Sheng-Chih Lin, Ali Keshavarzi, Siva Narendra and Vivek De
  IEEE International Electron Devices Meeting (IEDM), pp. 887-890, Washington DC, December 7-10, 2003.

• SETMOS: A Novel True Hybrid SET-CMOS High Current Coulomb Blockade Oscillation Cell for Future Nano-Scale Analog ICs
  Sananu Mahapatra, Vincent Pott, Serge Ecoffey, Alexandre Schmid, Christoph Wasshuber, Joseph W. Tringe, Yusuf Leblebici, Michel Declercq, Kaustav Banerjee and Adrian M. Ionescu
  IEEE International Electron Devices Meeting (IEDM), pp. 703-706, Washington DC, December 7-10, 2003.

• Nano, Quantum, and Molecular Computing: Are we Ready for the Validation and Test Challenges?
  Sandeep K. Shukla, Ramesh Karri, Seth C. Goldstein, Forrest Brewer, Kaustav Banerjee and Sankar Basu
  IEEE International High Level Design Validation and Test Workshop, pp. 3-7, November 12-14, San Francisco, CA, 2003.
  Invited

• A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits
  Santanu Mahapatra, Kaustav Banerjee, Florent Pegeon and Arian M. Ionescu
  IEEE International Conference on Computer-Aided Design (ICCAD), pp. 497-502, San Jose, CA, November 9-13, 2003.

• Nanometer Scale Issues for On-Chip Interconnections
  Kaustav Banerjee
  IUMRS-ICAM, Symposium B-1, Si-LSI-Related Materials, Processes and Characterization Technology, Yokohama, Japan, October 8-13, 2003.
  Invited

• Thermal Issues in Designing Nanometer Scale Interconnects
  Kaustav Banerjee
  20th International VLSI Multilevel Interconnection Conference (VMIC), Marina Del Rey, CA, September 22-25, 2003.
  Invited

• Teaching Microelectronics in the Silicon ICs Showstopper Zone: A Course on Ultimate Devices and Circuits: Towards Quantum Electronics
  Adrian M. Ionescu, Michel J. Declercq, Kaustav Banerjee and Santanu Mahapatra
  4th European Workshop on Microelectronics Education (EWME), Baiona, Mancomunidad de Vigo, Spain, May 23-24, 2003.

• An Interconnect Scaling Scheme with Constant On-Chip Inductive Effects
  Kaustav Banerjee and Amit Mehrotra
  International Journal of Analog Integrated Circuits and Signal Processing, Vol. 35, pp. 97–105, 2003.

• Modeling of Temperature Dependent Contact Resistance for Analysis of ESD Reliability
  Kwang-Hoon Oh, Jung-Hoon Chun, Kaustav Banerjee, Charvaka Duvvury and Robert W. Dutton
  41st IEEE Annual International Reliability Physics Symposium (IRPS), pp. 249-255, Dallas, TX, March 30-April 4, 2003.

• Analysis of IR-Drop Scaling with Implications for Deep Submicron P/G Network Designs
  Amir H. Ajami, Kaustav Banerjee, Amit Mehrotra and Massoud Pedram
  IEEE International Symposium on Quality Electronic Design (ISQED), pp. 35-40, San Jose, CA, March 24-26, 2003.

2002

• Via Design and Scaling Strategy for Nanometer Scale Interconnect Technologies
  Sungjun Im, Kaustav Banerjee and Kenneth E. Goodson
  Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 587-590, San Francisco, December 8-11, 2002.

• Non-uniform Conduction Induced Reverse Channel Length Dependence of ESD Reliability for Silicided NMOS Transistors
  Kwang-Hoon Oh, Kaustav Banerjee, Charvaka Duvvury and Robert W. Dutton
  Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 341-344, San Francisco, December 8-11, 2002.

• Modeling and Analysis of Power Dissipation in Single Electron Logic
  Santanu Mahapatra, Adrian M. Ionescu, Kaustav Banerjee and Michel J. Declercq
  Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 323-326, San Francisco, December 8-11, 2002.
• Analysis of Nonuniform ESD Current Distribution in Deep Submicron NMOS Transistors
  Kwang-Hoon Oh, Charvaka Duvvury, Kaustav Banerjee and Robert W. Dutton
  IEEE Transactions on Electron Devices, Vol. 49, No. 12, pp. 2171-2182, December 2002.

• Impact of Gate-to-Contact Spacing on ESD Performance of Salicided Deep Submicron NMOS Transistors
  Kwang-Hoon Oh, Charvaka Duvvury, Kaustav Banerjee and Robert W. Dutton
  IEEE Transactions on Electron Devices, Vol. 49, No. 12, pp. 2183-2192, December 2002.

• Analysis and Optimization of Substrate Noise Coupling in Single-Chip RF Transceiver Design
  Adil Koukab, Kaustav Banerjee and Michel Declercq
  IEEE International Conference on Computer-Aided Design (ICCAD), pp. 309-316, San Jose, CA, November 10-14, 2002.

• A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs
  Kaustav Banerjee and Amit Mehrotra
  IEEE Transactions on Electron Devices, Vol. 49, No. 11, pp. 2001-2007, November 2002.

• Quasi-Analytical Modeling of Drain Current and Conductance of Single Electron Transistors with MIB
  Santanu Mahapatra, Adrian M. Ionescu and Kaustav Banerjee
  32nd European Solid-State Device Research Conference (ESSDERC), pp. 391-394, Florence, Italy, September 24-26, 2002.

• Analysis and Design of Distributed ESD Protection Circuits for High-Speed Mixed-Signal and RF ICs
  Choshu Ito, Kaustav Banerjee and Robert W. Dutton
  IEEE Transactions on Electron Devices, Vol. 49, No. 8, pp. 1444-1454, August 2002.

• Analysis of On-Chip Inductance Effects for Distributed RLC Interconnects
  Kaustav Banerjee and Amit Mehrotra
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 8, pp. 904-915, August 2002.

• Power Dissipation Issues in Interconnect Performance Optimization for Sub-180 nm Designs
  Kaustav Banerjee and Amit Mehrotra
  IEEE Symposium on VLSI Circuits, pp. 12-15, Honolulu, HI, June 13-15, 2002.

• Few Electron Devices: Towards Hybrid CMOS-SET Integrated Circuits
  Adrian M. Ionescu, Michel J. Declercq, Santanu Mahapatra, Kaustav Banerjee and Jacques Gautier
  39th ACM Design Automation Conference (DAC), pp. 88-93, New Orleans, LA, June 10-14, 2002.
  Invited

• A Quasi-Analytical SET Model for Few Electron Circuit Simulation
  Santanu Mahapatra, Adrian Mihai Ionescu and Kaustav Banerjee
  IEEE Electron Device Letters, Vol. 23, No. 6, pp. 366-368, June 2002.

• Analysis of Gate-Bias-Induced Heating Effects in Deep-Submicron ESD Protection Designs
  Kwang-Hoon Oh, Charvaka Duvvury, Kaustav Banerjee and Robert W. Dutton
  IEEE Transactions on Devices, Materials and Reliability. Vol. 2, No. 2, pp. 36-42, June 2002.

• A SET Quantizer Circuit Aiming at Digital Communication System
  Santanu Mahapatra, Adrian M. Ionescu, Kaustav Banerjee and Michel J. Declercq
  IEEE International Symposium on Circuits and Systems (ISCAS), pp. 860-863, Scottsdale, AZ, May 26-29, 2002.

• SET-based Quantiser Circuit for Digital Communications
  Santanu Mahapatra, Adrian Mihai Ionescu, Kaustav Banerjee and Michel Declercq
  IEEE Electronics Letters, Vol. 38, No. 10, pp. 443-445, May 2002.

• Modeling and Analysis of Via Hot Spots and Implications for ULSI Interconnect Reliability
  Sungjun Im, Kaustav Banerjee and Kenneth E. Goodson
  40th IEEE Annual International Reliability Physics Symposium (IRPS), pp. 336-345, Dallas, TX, April 8-11, 2002.

• Investigation of Gate to Contact Spacing Effect on ESD Robustness of Salicided Deep Submicron Single Finger NMOS Transistors
  Kwang-Hoon Oh, Charvaka Duvvury, Kaustav Banerjee and Robert W. Dutton
  40th IEEE Annual International Reliability Physics Symposium (IRPS), pp. 148-155, Dallas, TX, April 8-11, 2002.

• Inductance Aware Interconnect Scaling
  Kaustav Banerjee and Amit Mehrotra
  IEEE International Symposium on Quality Electronic Design (ISQED), pp. 43-47, San Jose, CA, March 18-21, 2002.

• Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET (SG-MOSFET) with a Metal OverGate-Architecture
  Adrian M. Ionescu, Vincent Pott, Raphael Fritschi, Kaustav Banerjee, Michel J. Declercq, Philippe Renaud, Cyrille Hibert, Philippe Fluckiger and Georges A. Racine
  IEEE International Symposium on Quality Electronic Design (ISQED), pp. 496-501, San Jose, CA, March 18-21, 2002.

• 3-D Integrable Optoelectronic Devices for Telecommunications ICs
  Paolo Dainesi, Adrian M. Ionescu, Luc Thevenaz, Kaustav Banerjee, Michel J. Declercq, Philippe Robert, Philippe Renaud, Philippe Fluckiger, Cyrille Hibert and Georges A. Racine
  IEEE International Solid State Circuits Conference (ISSCC), pp. 360-361, San Francisco, CA, February, 4-6, 2002.

• Analytical Thermal Model for Multilevel VLSI Interconnects Incorporating Via Effect
  Ting-Yen Chiang, Kaustav Banerjee and Krishna C. Saraswat
  IEEE Electron Device Letters, Vol. 23, No. 1, pp. 31-33, Jan. 2002.

2001

• Localized Heating Effects and Scaling of Sub-0.18 Micron CMOS Devices
  Eric Pop, Kaustav Banerjee, Per Sverdrup, Robert Dutton and Kenneth Goodson
  Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 677-680, Washington, DC, December 3-5, 2001.

• Gate Bias Induced Heating Effect and Implications for the Design of Deep Submicron ESD Protection
  Kwang-Hoon Oh, Charvaka Duvvury, Kaustav Banerjee and Robert W. Dutton
  Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 315-318, Washington, DC, December 3-5, 2001.

• Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects
  Ting-Yen Chiang, Kaustav Banerjee and Krishna C. Saraswat
  IEEE International Conference on Computer-Aided Design (ICCAD), pp. 165-172, San Jose, CA, November 4-8, 2001.

• Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets
  Kaustav Banerjee and Amit Mehrotra
  IEEE International Conference on Computer-Aided Design (ICCAD), pp. 158-164, San Jose, CA, November 4-8, 2001.

• Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion
  Amir H. Ajami, Kaustav Banerjee and Massoud Pedram
  IEEE International Conference on Computer-Aided Design (ICCAD), pp. 44-48, San Jose, CA, November 4-8, 2001.

• Interconnect Reliability under ESD Conditions: Physics, Models and Design Guidelines
  Kaustav Banerjee
  23rd Annual EOS/ESD Symposium, pp. 191, Portland, Oregon, September 9-13, 2001.

• Analysis and Optimization of Distributed ESD Protection Circuits for High-Speed Mixed Signal and RF Applications
  Choshu Ito, Kaustav Banerjee and Robert W. Dutton
  23rd Annual EOS/ESD Symposium, pp. 355-363, Portland, OR, September 9-13, 2001.

• Global(Interconnect)Warming
  Kuastav Banerjee and Amit Mehrotra
  IEEE Circuits and Devices Magazine, Vol. 17, Issue 5, pp. 16-32, September 2001.
  Invited

• <Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects
  Kaustav Banerjee and Amit Mehrotra
  38th ACM Design Automation Conference (DAC), pp. 798-803, Las Vegas, NV, June 18-22, 2001.
  Best Paper Award

• Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs
  Amir H. Ajami, Kaustav Banerjee, Massoud Pedram and Lukas P.P.P. van Ginneken
  38th ACM Design Automation Conference (DAC), pp. 567-572, Las Vegas, NV, June 18-22, 2001.

• Accurate Analysis of On-Chip Inductance Effects and Implications for Optimal Repeater Insertion and Technology Scaling
  Kaustav Banerjee and Amit Mehrotra
  IEEE Symposium on VLSI Circuits, pp. 195-198, Kyoto, Japan, June 14-16, 2001.

• Non-Uniform Chip-Temperature Dependent Signal Integrity
  Amir H. Ajami, Kaustav Banerjee and Massoud Pedram
  IEEE Symposium on VLSI Technology, pp. 145-146, Kyoto, Japan, June 12-14, 2001.

• A New Analytical Thermal Model for Multilevel VLSI Interconnects Incorporating Via Effects
  Ting-Yen Chiang, Kaustav Banerjee and Krishna C. Saraswat
  IEEE International Interconnect Technology Conference (IITC), pp. 92-94, San Francisco, CA, June 4-6, 2001.

• RF LDMOS Characterization and Its Compact Modeling
  Jaejune Jang, Olof Tornblad, Torkel Arnborg, Qiang Chen, Kaustav Banerjee, Zhiping Yu and Robert W. Dutton
  IEEE/MTT-S International Microwave Symposium, pp. 967-970, Phoenix, AZ, May 20-25, 2001.

• 3-D Heterogeneous ICs: A Technology for the Next Decade and Beyond
  Kaustav Banerjee, Shukri J. Souri, Pawan Kapur and Krishna C. Saraswat
  5th IEEE Workshop on Signal Propagation on Interconnects, Venice, Italy, May 13-16, 2001.

• A Fast Analytical Technique for Estimating the Bounds of On-Chip Clock Wire Inductance
  Yi-Chang Lu, Kaustav Banerjee, Mustafa Celik and Robert W. Dutton
  IEEE Custom Integrated Circuits Conference (CICC), pp. 241-244, San Diego, CA, May 6-9, 2001.

• Effects of Non-Uniform Substrate Temperature on the Clock Signal Integrity in High Performance Designs
  Amir H. Ajami, Massoud Pedrarn and Kaustav Banerjee
  IEEE Custom Integrated Circuits Conference (CICC), pp. 233-236, San Diego, CA, May 6-9, 2001.

• 3-D ICs: A Novel Chip Design for Improving Deep Submicrometer Interconnect Performance and Systems-on-Chip Integration
  Kaustav Banerjee, Shukri J. Souri, Pawan Kapur and Krishna C. Saraswat
  Proceedings of the IEEE, Special Issue, Interconnections- Addressing The Next Challenge of IC Technology, Vol. 89, No. 5, pp. 602-633, May 2001.
  Invited

• Non-uniform Bipolar Conduction in Single Finger NMOS Transistors and Implications for Deep Submicron ESD Design
  Kwang-Hoon Oh, Charvaka Duvvury, Craig Salling, Kaustav Banerjee and Robert W. Dutton
  39th IEEE Annual International Reliability Physics Symposium (IRPS), pp. 226-234, Orlando, FL, April 30-May 3, 2001.

• Analysis and Optimization of Thermal Issues in High-Performance VLSI
  Kaustav Banerjee, Massoud Pedram and Amir H. Ajami
  ACM/SIGDA International Symposium on Physical Design (ISPD), pp. 230-237, Sonoma, CA, April 1-4, 2001.
  Invited

• Analysis and Design of ESD Protection Circuits for High-Frequency/RF Applications
  Choshu Ito, Kaustav Banerjee and Robert W. Dutton
  IEEE International Symposium on Quality Electronic Design (ISQED), pp. 117-122, San Jose, CA, March 26-28, 2001.

• Trends for ULSI Interconnections and Their Implications for Thermal, Reliability and Performance Issues
  Kaustav Banerjee
  Seventh International Dielectrics and Conductors for ULSI Multilevel Interconnection Conference (DCMIC), pp. 38-50, Santa Clara, CA, March 5-9, 2001.
  Invited

• Interconnect Limits on Gigascale Integration (GSI) in the 21st Century
  Jeffrey A. Davis, Raguraman Venkatesan, Alain Kaloyeros, Michael Beylansky, Shukri J. Souri, Kaustav Banerjee, Krishna C. Saraswat, Arifur Rahman, Rafael Reif and James. D. Meindl
  Proceedings of the IEEE, Special Issue on Limits of Semiconductor Technology, Vol. 89, No. 3, pp. 305- 324, March 2001.
  Invited

2000

• Effect of Via Separation and Low-k Dielectric Materials on the Thermal Characteristics of Cu Interconnects
  Ting-Yen Chiang, Kaustav Banerjee and Krishna C. Saraswat
  Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 261-264, San Francisco, CA, Dec. 11-13, 2000.

• Full Chip Thermal Analysis of Planar (2-D) and Vertically Integrated (3-D) High Performance ICs
  Sungjun Im and Kaustav Banerjee
  Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 727-730, San Francisco, CA, Dec. 11-13, 2000.

• Thermal Effects in ULSI Interconnects
  Kaustav Banerjee
  Fabless Semiconductor Association (FSA) Design Modeling Workshop, Santa Clara, CA, Oct. 11-12, 2000.
  Invited Tutorial

• Advanced Electro-Thermal Modeling and Simulation Techniques for Deep Sub-Micron Devices
  Per G. Sverdrup, Olof Tornblad, Kaustav Banerjee, Daniel Yergeau, Zhiping Yu, Robert W. Dutton and Kenneth E. Goodson
  Proceedings of TECHCON, Phoenix, AZ, Sept. 21-23, 2000.

• 3-D ICs: Motivation, Performance Analysis, and Technology
  Krishna C. Saraswat, Kaustav Banerjee, Amol R. Joshi, Pranav Kalavade, Pawan Kapur and Shukri J. Souri
  Proc. 26th European Solid-State Circuits Conference (ESSCIRC ‘2000), Stockholm, Sweden, Sept. 19 - 21, 2000.
  Invited

• Sub-Continuum Thermal Simulations of Deep Sub-micron Devices under ESD Conditions
  Per G. Sverdrup, Kaustav Banerjee, Changhong Dai, Wei-kai Shih, Robert W. Dutton and Kenneth E. Goodson
  IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 54-57, Sept. 6-8, Seattle, WA, 2000.

• Multiple Si Layer ICs: Motivation, Performance Analysis, and Design Implications
  Shukri J. Souri, Kaustav Banerjee, Amit Mehrotra and Krishna C. Saraswat
  37th ACM Design Automation Conference (DAC), pp. 213-220, June 5-9, Los Angeles, CA, 2000.

• 3-D lCs with Multiple Si Layers: Performance Analysis, and Technology
  Krishna C. Saraswat, Kaustav Banerjee, Amol R. Joshi. Pranav Kalavade, Shukri J. Souri and V. Subramanian
  197th Meeting of The Electrochemical Society, Toronto, May 14-18, 2000.
  Invited

• Thermal Characteristics of Sub-Micron Vias Studied by Scanning Joule Expansion Microscopy
  Masanobu Igeta, Kaustav Banerjee, Guanghua Wu, Chenming Hu and Arun Majumdar
  IEEE Electron Device Letters, Vol. 21, No. 5, pp. 224-226, May 2000.

• Process and Layout Dependent Substrate Resistance Modeling for Deep Sub-Micron ESD Protection Devices
  Xin Y. Zhang, Kaustav Banerjee, Ajith Amerasekera, Vikas Gupta, Zhiping Yu and Robert W. Dutton
  38th IEEE Annual International Reliability Physics Symposium Proceedings (IRPS), pp. 295-303, San Jose, CA, April 10- 13, 2000.

• Quantitative Projections of Reliability and Performance for Low-k/Cu Interconnect Systems
  Kaustav Banerjee, Amit Mehrotra, William Hunter, Krishna C. Saraswat, Kenneth E. Goodson and S. Simon Wong
  38th IEEE Annual International Reliability Physics Symposium Proceedings (IRPS), pp. 354-358, San Jose, CA, April 10- 13, 2000.

• Microanalysis of VLSI Interconnect Failure Modes under Short-pulse Stress Conditions
  Kaustav Banerjee, Dae Yong Kim, Ajith Amerasekera, Chenming Hu, S. Simon Wong and Kenneth E. Goodson
  38th IEEE Annual International Reliability Physics Symposium Proceedings (IRPS), pp. 283-288, San Jose, CA, April 10-13, 2000.

• Performance Analysis and Technology of 3-D ICs
  Krishna C. Saraswat, Shukri J. Souri, Kaustav Banerjee and Pawan Kapur
  ACM International Workshop on System Level Interconnect Prediction (SLIP), pp. 85-90, San Diego, CA, April 8-9, 2000.
  Invited

• Thermal Effects in Deep Sub-Micron VLSI Interconnects
  Kaustav Banerjee
  IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 20-22, 2000.
  Invited Tutorial

Before 2000

• Thermal Effects in Deep Sub-micron VLSI Interconnects and Implications for Reliability and Performance
  Kaustav Banerjee
  Electronics Research Laboratory, Memorandum no. UCB/ERL M99/48, September 22, 1999.

• On Thermal Effects in Deep Sub-Micron VLSI Interconnects
  Kaustav Banerjee, Amit Mehrotra, Alberto Sangiovanni-Vincentelli and Chenming Hu
  36th ACM Design Automation Conference (DAC), pp. 885-891, New Orleans, LA, June 21-25, 1999.

• Investigation of Self-Heating Phenomenon in Small Geometry Vias Using Scanning Joule-Expansion Microscopy
  Kaustav Banerjee, Guanghua Wu, Massanobu Igeta, Ajith Amerasekera, Arun Majumdar and Chenming Hu
  37th IEEE Annual International Reliability Physics Symposium Proceedings (IRPS), pp. 297-302, San Diego, CA, March 23-25, 1999.

• Comparison of E and 1/E TDDB Model for SiO₂ under Long-Term/Low-Field Test Conditions
  Joe W. McPherson, Vijay Reddy, Kaustav Banerjee and Huy Le
  Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 171-174, San Francisco, CA, Dec. 6-9, 1998.

• A New Quantitative Model for Deep Submicron Contact Resistance
  Kaustav Banerjee, Ajith Amerasekara, Girish Dixit and Chenming Hu
  Proceedings of the SRC TECHCON, Las Vegas, NV, 1998.

• Thermal Effects in Interconnects
  William Hunter, W-Y. Shih and Kaustav Banerjee
  IEEE Annual International Reliability Physics Symposium (IRPS), Reno, NV, March 30 - April 2, 1998.
  Invited Tutorial

• High Current Effects in Silicide films for Sub-0.25 micron VLSI Technologies
  Kaustav Banerjee, Ajith Amerasekera, Jorge A. Kittl and Chenming Hu
  36th Proceedings of the IEEE Annual International Reliability Physics Symposium (IRPS), pp. 284-292, Reno, NV, March 30 – April 2, 1998.

• Characterization of Self-Heating in Advanced VLSI Interconnect Lines Based on Thermal Finite Element Simulation
  Sven Rzepka, Kaustav Banerjee, Ekkehard Meusel and Chenming Hu
  IEEE Transactions on Components, Packaging, and Manufacturing Technology-A, Vol. 21, No. 3, pp. 406-411, 1998.

• Temperature and Current Effects on Small-Geometry-Contact Resistance
  Kaustav Banerjee, Ajith Amerasekera, Girish Dixit and Chenming Hu
  Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 115 -118, Washington DC, Dec. 7-10, 1997.

• High Current Effects in Metal Interconnects
  Kaustav Banerjee, Ajith Amerasekera, Girish Dixit and Chenming Hu
  Proceedings of the SRC Topical Research Conference on Reliability, Vanderbilt University, Nashville, Oct. 21-22, 1997.
  Invited

• Characterization of Self-Heating in Advanced VLSI Interconnect Lines Based on Thermal Finite Element Simulation
  Sven Rzepka, Kaustav Banerjee, Ekkehard Meusel and Chenming Hu
  3rd International Workshop on Thermal Investigations of ICs and Microstructures (THERMINIC), pp. 108-113, Cannes / Cote d'Azur, France, Sept. 21-23, 1997.

• High-Current Failure Model for VLSI Interconnects Under Short-PuIse Stress Conditions
  Kaustav Banerjee, Ajith Amerasekera, Nathan Cheung and Chenming Hu
  IEEE Electron Device Letters, Vol. 18, No. 9, pp. 405-407, 1997.

• Characterization of Contact and Via Failure under Short Duration High Pulsed Current Stress
  Kaustav Banerjee, Ajith Amerasekera, Girish Dixit, Nathan Cheung and Chenming Hu
  35th Proceedings of the IEEE Annual International Reliability Physics Symposium (IRPS), pp. 216-220, Denver, CO, April 8-10, 1997.

• Failure Mechanisms of Multi Layered Thin Film Metal Interconnects under a High Current Pulse
  Kaustav Banerjee, Ajith Amerasekera, Nathan Cheung and Chenming Hu
  MRS Spring Symp., San Francisco, CA, March 31-April 4, 1997.

• The Effect of Interconnect Scaling and Low-k Dielectric on the Thermal Characteristics of the IC Metal
  Kaustav Banerjee, Ajith Amerasekera, Girish Dixit and Chenming Hu
  Technical Digest IEEE International Electron Devices Meeting (IEDM), pp. 65-68, San Francisco, CA, Dec. 8-11, 1996.

• The Dependence of W-plug Via EM Performance on Via Size
  Huy A. Le, Kaustav Banerjee and Joe W. McPherson
  Semiconductor Science and Technology, Vol. 11, pp. 858-864, 1996.

• Thermal Analysis of the Fusion Limits of Metal Interconnect under Short Duration Current Pulses
  Kaustav Banerjee, Sven Rzepka, Ajith Amerasekera, Nathan Cheung and Chenming Hu
  Final Report, IEEE International Integrated Reliability Workshop (IRW), pp. 98-102, Lake Tahoe, CA, Oct 20-23, 1996.

• Characterization and Simulation of Self Heating in a Multi Level VLSI Interconnect System under DC and Pulsed Current Conditions
  Kaustav Banerjee, Sven Rzepka, Ajith Amerasekera and Chenming Hu
  Proceedings of the SRC TECHCON, Phoenix, AZ, Sept. 1996.

• Impact of High Current Stress Conditions on VLSI Interconnect Electromigration Reliability Evaluation
  Kaustav Banerjee, L. Ting, Nathan Cheung and Chenming Hu
  Proceedings of the Thirteenth International VLSI Multilevel Interconnection Conference (VMIC), pp. 289- 294, Santa Clara, CA, June 18-20, 1996.

• Characterization of VLSI Circuit Interconnect Heating and Failure under ESD Conditions
  Kaustav Banerjee, Ajith Amerasekera and Chenming Hu
  34th Proceedings of the IEEE Annual International Reliability Physics Symposium (IRPS), pp. 237-245, Dallas, TX, April 30-May 2, 1996.