High Speed Digital Integrated Circuit Design

Course Description:

Nanometer scale issues in digital VLSI design: Scaled CMOS devices and technologies including high-k/metal gate, strained-Si, channel and substrate engineering, ultra-thin-body SOI, double-gate (FinFETs) and multi-gate FETs including nanosheet-FETs, nanowire-FETs, Schottky- and ballistic-FETs; device-circuit co-design for non-classical CMOS technologies; clock and power distribution; nanoscale circuit/system design issues including variability, thermal management, interconnects, and reliability; principles of ultra low-power design, subthreshold design and sub-kT/q operation--tunnel-FETs, NEM-FETs, IMOS etc; emerging memory technologies; heterogeneous integration using 3D ICs; neuromorphic ICs.

Recommended Prerequisites: