We have highlighted an underlying physical concept behind the BTBT process that has been mostly overlooked in literature. It has been shown that ignoring the dual nature of electrons and holes during the BTBT phenomenon can not only lead to substantially erroneous results but also to misleading...
Kaustav Banerjee is a Professor of Electrical and Computer Engineering and Director of the Nanoelectronics Research Lab at UC Santa Barbara. He is also an Affiliated Faculty with the California NanoSystems Institute (CNSI) and the Institute for Energy Efficiency (IEE) at UCSB. Initially trained as a physicist, he received the Ph.D. degree in Electrical Engineering and Computer Sciences (with minors in Physics and Materials Science) from the University of California, Berkeley, in 1999, working with Prof. Chenming Hu.
His research interests include nanometer scale issues in CMOS VLSI as well as circuits and systems issues in emerging nanoelectronics. He is currently involved in exploring the physics, technology, and applications of carbon nanomaterials for next-generation green electronics.
Prior to joining UCSB, he was with Stanford University (1999-2001) as a Research Associate at the Center for Integrated Systems with joint appointments from the EE Department and the Thermosciences Division of the ME Department. He has also held a number of summer/visiting positions at Texas Instruments, Dallas (1993-97); École Polytechnique Fédérale de Lausanne, Switzerland (2001); and the Circuits Research Laboratories, Intel Corporation, Hillsboro, Oregon (2002). In December 2010, he held a Visiting Professorship at the Tokyo Institute of Technology, Japan.
Prof. Banerjee has made seminal contributions in almost every area he has worked on, and his technical ideas and innovations have seen wide-spread proliferation both in the industry and academia as exemplified by his h-index of 40 (from Google Scholar) as of Jan 2012. His doctoral research at Berkeley and subsequent work at Stanford on thermal issues in integrated circuits played a pioneering role in introducing the concept of “thermal integrity”, which set the foundation for Gradient Design Automation, the first company to introduce temperature-aware IC design technology in the Electronic Design Automation Industry. He has also made a number of key contributions in the area of nanoscale IC interconnects and innovative interconnect solutions including 3-D ICs and carbon-based interconnects, which have helped shape the semiconductor industry's R&D efforts in those areas.
Prof. Banerjee’s research is chronicled in over 250 journal articles, international refereed conference papers and book chapters, including over 50 invited papers. He is also a Co-editor of the book Emerging Nanoelectronics: Life With and After CMOS (Springer-Verlag, 2004). He has delivered over 100 keynote/panel speeches, tutorials, and invited talks at major international forums and academic/research institutes around the world. His works have been highly cited and used by other researchers in the field. According to Google Scholar, his top-10 papers average over 200 citations, as of Jan 2012. His exceptional research accomplishments and inspirational teaching led to his appointment as Full Professor in 2007, within 5 years of his joining UCSB as Assistant Professor in 2002. He has also been recognized with numerous awards and honors.
Prof. Banerjee has served on the technical program committees of nearly every leading IEEE and ACM conferences in his area including IEDM, DAC, ICCAD, IRPS and SISPAD. He has also served on the organizing committee of ISQED at various positions including Technical Program Chair (2002) and General Chair (2005). From 2005-2008 he served on the IEEE EDS Nanotechnology Committee. At present, he serves on the IEEE/EDS VLSI Technology and Circuits Committee. Since 2008, he has been a Distinguished Lecturer of the IEEE Electron Devices Society. Prof. Banerjee was elected a Fellow of IEEE in 2011.