We have highlighted an underlying physical concept behind the BTBT process that has been mostly overlooked in literature. It has been shown that ignoring the dual nature of electrons and holes during the BTBT phenomenon can not only lead to substantially erroneous results but also to misleading...
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Chuan Xu, Navin Srivastava, Roberto Suaya and Kaustav Banerjee, "Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs with Multiple Substrates," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, No. x, pp. xx-yy, 2012 (to appear).
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H. Li, C. Russ, W. Liu, D. Johnsson, H. Gossner and K. Banerjee, "ESD Characterization of Atomically-Thin Graphene," 34th Annual EOS/ESD Symposium, Tucson, AZ, September 9-14, 2012 (to appear).
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C. Xu, R. Suaya and K. Banerjee, "Fast Extraction of High-Frequency Parallel Admittance of Through-Silicon-Vias and their Capacitive Coupling-Noise to Active Regions," IEEE International Microwave Symposium, Montréal, Canada, June 17-22, 2012 (to appear).
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Deblina Sarkar and Kaustav Banerjee, "Proposal for Tunnel-Field-Effect-Transistor as Ultra-Sensitive and Label-Free Biosensors," Applied Physics Letters, 100, No. 14, 143108, 2012.
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C. Xu and K. Banerjee, "Compact Capacitance and Capacitive Coupling-Noise Modeling of Through-Oxide Vias in FDSOI Based Ultra-High Density 3-D ICs," IEEE International Electron Devices Meeting (IEDM), pp. 817-820, Washington DC, Dec. 5-7, 2011.
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Wei Liu, Hong Li, Chuan Xu, Yasin Khatami and Kaustav Banerjee, "Synthesis of High-Quality Monolayer and Bilayer Graphene on Copper using Chemical Vapor Deposition," CARBON, Vol. 49, No. 13, pp. 4122-4130, Nov. 2011.
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Xiang Li, Zhixian Chen, Nansheng Shen, Deblina Sarkar, Navab Singh, Kaustav Banerjee, Guo-Qiang Lo and Dim-Lee Kwong, "Vertically Stacked and Independently Controlled Twin-Gate MOSFETs on a Single Si-Nanowire," IEEE Electron Device Letters, Vol. 32, No. 11, pp. 1492-1494, Nov. 2011.
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Ramanathan Gandhi, Zhixian Chen, Navab Singh, Kaustav Banerjee and Sungjoo Lee, "CMOS Compatible Vertical Silicon Nanowire Gate-All-Around p-type Tunneling FETs with ≤50 mV/decade Subthreshold Swing," IEEE Electron Device Letters, Vol. 32, No. 11, pp. 1504-1506, Nov. 2011.
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Chuan Xu, Roberto Suaya and Kaustav Banerjee, "Compact Modeling and Analysis of Through-Si-Via Induced Electrical Noise Coupling in 3-D ICs," IEEE Transactions on Electron Devices, Vol. 58, No. 11, pp. 4024-4034, Nov. 2011.
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Seid Hadi Rasouli, Chuan Xu, Navab Singh and Kaustav Banerjee, "A Physical Model for Work-Function Variation in Ultra-Short Channel Metal-Gate MOSFETs," IEEE Electron Device Letters, Vol. 32, No. 11, pp. 1507-1509, Nov. 2011.
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Chuan Xu, Vassilis Kourkoulos, Roberto Suaya and Kaustav Banerjee, "A Fully Analytical Model for the Series Impedance of Through-Silicon Vias with Consideration of Substrate Effects and Coupling with Horizontal Interconnects," IEEE Transactions on Electron Devices, Vol. 58, No. 10, pp. 3529-3540, Oct. 2011.
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Deblina Sarkar and Kaustav Banerjee, "Metallic-Nanoparticle Assisted Enhanced Band-to-Band Tunneling Current," Applied Physics Letters, Vol. 99, No. 13, p. 133116, Sept 26, 2011.
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Hong Li, Navin Srivastava, Jun-Fa Mao, Wen-Yan Yin and Kaustav Banerjee, "Carbon Nanotube Vias: Does Ballistic Electron-Phonon Transport Imply Improved Performance and Reliability?," IEEE Transactions on Electron Devices, Vol. 58, no. 8, pp. 2689-2701, Aug. 2011.
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Seid Hadi Rasouli, Kazuhiko Endo, Jone F. Chen, Navab Singh and Kaustav Banerjee, "Grain-Orientation Induced Quantum Confinement Variation in FinFETs and Multi-Gate Ultra-Thin Body CMOS Devices and Implications for Digital Design," IEEE Transactions on Electron Devices, Special Issue on "Characterization of Nano CMOS Variability by Simulation and Measurements", Vol. 58, no. 8, pp. 2282-2292, Aug. 2011.
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H. F. Dadgour, M. M. Hussain, A. Cassell, N. Singh and K. Banerjee, "Impact of Scaling on the Performance and Reliability Degradation of Metal-Contacts in NEMS Devices," IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, April 10-14, pp. 280-289, 2011.
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Ramanathan Gandhi, Zhixian Chen, Navab Singh, Kaustav Banerjee, and Sungjoo Lee, "Vertical Si-Nanowire n-Type Tunneling FETs With Low Subthreshold Swing (≤ 50 mV/decade) at Room Temperature," IEEE Electron Device Letters, vol. 32, no. 4, pp. 437-439, April 2011
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D. Sarkar, C. Xu, H. Li, and K. Banerjee, "High-Frequency Behavior of Graphene-Based Interconnects—Part I: Impedance Modeling," IEEE Trans. Electron Devices, vol. 58, no. 3, pp. 843-852, March 2011
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D. Sarkar, C. Xu, H. Li, and K. Banerjee, "High-Frequency Behavior of Graphene-Based Interconnects—Part II: Impedance Analysis and Implications for Inductor Design," IEEE Trans. Electron Devices, vol. 58, no. 3, pp. 853-859, March. 2011